UNIVERSITY OF ENGINEERING

AND TECHNOLOGY, TAXILA

Lab Report 10
Digital System Design Lab
Name: Maham Zaman

Reg No.: 19-CP-25

Section: Alpha

Department: Computer Engineering

Submitted To: Sir Asghar Ismail\

Objective:
Verilog Code for Complete Module Stitching Datapath and Control Unit of Traffic Light Controller
using ASMD Technique

Apparatus List:
PC installed with Vivado Xilinx tool Nexys
4 Fpga Kit

Procedure:
Following is Procedure for Implementation on FPGA kit
1. Writing the Source Code of module and simulating it
2. Opening Elaborated Design
3. Setting Constraints
4. Running Synthesis
5. After Successful Synthesis Running Implementation
6. After Successful Implementation Generating Bit Stream
7. Downloading Bit Stream to FPGA kit using Hardware Manager

Lab Task:
Write Verilog Code for Complete Module Stitching Datapath and Control Unit of Traffic Light
Controller using ASMD Technique

Verilog Code for Top Module of TLC:

module TLC(output [1:0] TLC_SigEast, output [1:0] TLC_SigWest, output [1:0] TLC_SigNorth,
output [1:0]TLC_SigSouth, input TLC_RST,input Clk);
wire W_COD0_SigWest, W_COD0_SigEast,W_COD0_SigNorth,W_COD0_SigSouth,
W_COD0_Counter;
CU_TLC C0(.Clk(Clk),.CU_RST(TLC_RST),.CU_CountFlag(W_COD0_Counter),
.CU_SelEast(W_COD0_SigEast), .CU_SelWest(W_COD0_SigWest),
.CU_SelNorth(W_COD0_SigNorth) , .CU_SelSouth(W_COD0_SigSouth));
DP_TLC D0(.Clk(Clk),.DP_CountFlag(W_COD0_Counter),.DP_SelEast(W_COD0_SigEast),
.DP_SelWest(W_COD0_SigWest),.DP_SelNorth(W_COD0_SigNorth),
.DP_SelSouth(W_COD0_SigSouth), .DP_SigEast(TLC_SigEast),
.DP_SigWest(TLC_SigWest), .DP_SigNorth(TLC_SigNorth), .DP_SigSouth(TLC_SigSouth));
endmodule
Verilog Code for Control Unit of TLC: State
Transition:
module CU_TLC(output reg CU_SelEast,output reg CU_SelWest,output reg CU_SelNorth,
output reg CU_SelSouth, input CU_RST, input Clk,input CU_CountFlag);
parameter S_Rst=3’b000,S_East=3’b001,S_West=3’b010,S_North=3’b011,S_South=3’b100;
reg[2:0]State_Reg;
always@(posedge Clk or negedge CU_RST)
if(RST==0) State_Reg<=S_Rst;
else
case( State_Reg) S_Rst:
State_Reg<=S_West;
S_West:
if(Count_Flag==1)
State_Reg<=S_North;
else
State_Reg<=S_West; S_North:
if(Count_Flag==1)
State_Reg<=S_East;
else
State_Reg<=S_North;
S_East:
if(Count_Flag==1)
State_Reg<=S_South;
else
State_Reg<=S_East; S_South:
if(Count_Flag==1)
State_Reg<=S_West;
else
State_Reg<=S_South;
endcase
endmodule
Signal Assignment:
module CU_TLC(output reg CU_SelEast,output reg CU_SelWest,output reg CU_SelNorth,
output reg CU_SelSouth, input CU_RST, input Clk,input CU_CountFlag); parameter
S_Rst=3’b000,S_East=3’b001,S_West=3’b010,S_North=3’b011,S_South=3’b100;
reg[2:0]State_Reg;

always@(State_Reg) case(State_Reg) S_Rst:

begin
CU_SelEast<=1’b0;CU_SelNorth<=1’b0;
CU_SelSouth<=1’b01; CU_SelWest<=1’b 0;
end
S_West:
begin
CU_SelSouth<=1’b 0;CU_SelWest<=1’b 1;
end
S_North:
begin
CU_SelNorth<=1’b1; CU_SelWest<=1’b0;
end S_East:
begin
CU_SelEast<=1’b1; CU_SelNorth<=1’b0;
end
S_South:
begin
CU_SelSouth<=1’b1;CU_SelEast<=1’b0;
end

endmodule

Verilog Code for Datapath of TLC:

module DP_TLC(output [1:0]DP_South, output [1:0]DP_North, output [1:0]DP_East,
output [1:0]DP_West,input DP_CLK, input DP_Rst, input CU_North, input CU_South,
input CU_East, input CU_West, output CU_CFlag); wire [1:0] Green; wire [1:0] Red;
assign Green=2'b01;
assign Red=2'b10;
Mux21 M_East(.Mux_Out(DP_East),.Mux_In1(Red),.Mux_In2(Green),
.Mux_Sel(CU_East));
Mux21 M_West(.Mux_Out(DP_West),.Mux_In1(Red),.Mux_In2(Green),
.Mux_Sel(CU_West));
Mux21 M_South(.Mux_Out(DP_South),.Mux_In1(Red),.Mux_In2(Green),
.Mux_Sel(CU_South) );
Mux21 M_North(.Mux_Out(DP_North),.Mux_In1(Red),.Mux_In2(Green),
.Mux_Sel(CU_North) );
Counter C1(.Count_Flag(CU_CFlag), .Count_Clk(DP_CLK), .Count_Rst(DP_Rst));
endmodule
Code for Mux:
module Mux21(output [1:0] Mux_Out,input [1:0] Mux_In1,input [1:0] Mux_In2,
input Mux_Sel ); assign Mux_Out = (Mux_Sel)? Mux_In1: Mux_In2;
endmodule

Code for Counter:

module Counter(output reg Count_Flag, input Count_Clk, input Count_Rst);
reg [2:0] Count; always@(posedge Count_Clk or posedge Count_Rst)
if(Count_Rst==1) begin
Count_Flag=1'b0;
Count=3'd0; end
else
if(Count==3'd4)
Count_Flag=1'b1;
else if(Count==3'd5)
begin
Count_Flag=1'b0;
Count=3'd0;
end else
Count=Count+1;
endmodule

Schematic Diagram:

FPGA Implementation: