Professional Documents
Culture Documents
COLOR TELEVISION
CN27E90, CX32E70
CN32E90, CN35E15
CF35E50, CX35E60
CX35E70, CX35E81
CN35E90, CN35E95
SECTION II
TUNER, IF/MTS/S.PRO MODULE ......................... 16
1. CIRCUIT BLOCK ............................................................................................................................. 17
2. TUNER ................................................................................................................................................ 18
3. IF/MTS/S.PRO MODULE ................................................................................................................. 19
4. PIP TUNER ......................................................................................................................................... 23
SECTION III
CHANNEL SELECTION CIRCUIT ........................ 24
1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM .................................................... 25
2. OPERATION OF CHANNEL SELECTION CIRCUIT ................................................................ 25
3. MICROCOMPUTER ......................................................................................................................... 26
4. MICROCOMPUTER TERMINAL FUNCTION ........................................................................... 27
5. EEPROM (QA02) ............................................................................................................................... 29
6. ON SCREEN FUNCTION ................................................................................................................. 29
7. SYSTEM BLOCK DIAGRAM ......................................................................................................... 30
8. LOCAL KEY DETECTION METHOD .......................................................................................... 31
9. REMOTE CONTROL CODE ASSIGNMENT ............................................................................... 32
10. ENTERING TO SERVICE MODE ................................................................................................ 35
11. TEST SIGNAL SELECTION ......................................................................................................... 35
12. SERVICE ADJUSTMENT .............................................................................................................. 35
13. FAILURE DIAGNOSIS PROCEDURE ......................................................................................... 36
14. TROUBLE SHOOTING CHART .................................................................................................. 38
SECTION IV
AUDIO OUTPUT CIRCUIT ..................................... 41
1. OUTLINE ............................................................................................................................................ 42
2. AUDIO OUT IC .................................................................................................................................. 43
2
SECTION V
A/V SWITCHING CIRCUIT .................................... 44
1. OUTLINE ............................................................................................................................................ 45
2. IN / OUT TERMINALS ..................................................................................................................... 45
3. CIRCUIT OPERATION .................................................................................................................... 45
SECTION VI
VIDEO PROCESSING CIRCUIT ............................ 47
1. OUTLINE ............................................................................................................................................ 48
2. SIGNAL FLOW .................................................................................................................................. 48
3. CIRCUIT OPERATION .................................................................................................................... 48
SECTION VII
V/C/D/IC ...................................................................... 52
1. OUTLINE ............................................................................................................................................ 53
2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE
CONTROLS ...................................................................................................................................... 53
3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE.......................... 53
4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE................................. 53
5. LOW COST OF IC ............................................................................................................................ 53
SECTION VIII
PIP MODULE ............................................................. 55
SECTION IX
SYNC SEPARATION, H-AFC,
H-OSCILLATOR CIRCUITS .............................. 58
1. SYNC SEPARATION CIRCUIT ...................................................................................................... 59
2. H AFC (Automatic Frequency Control) CIRCUIT ......................................................................... 60
3. H OSCILLATOR CIRCUIT ............................................................................................................. 61
SECTION X
VERTICAL OUTPUT CIRCUIT ............................. 63
1. OUTLINE ............................................................................................................................................ 64
2. V OUTPUT CIRCUIT ....................................................................................................................... 65
3
SECTION XI
HORIZONTAL DEFLECTION CIRCUIT.............. 69
1. OUTLINE ............................................................................................................................................ 70
2. HORIZONTAL DRIVE CIRCUIT ................................................................................................... 70
3. BASIC OPERATION OF HORIZONTAL DRIVE ........................................................................ 71
4. HORIZONTAL OUTPUT CIRCUIT ............................................................................................... 74
5. HIGH VOLTAGE GENERATION CIRCUIT ................................................................................. 79
6. X-RAY PROTECTION CIRCUIT ................................................................................................... 82
7. OVER CURRENT PROTECTION CIRCUIT................................................................................ 83
8. KINK CORRECTION CIRCUIT ..................................................................................................... 84
SECTION XII
DEFLECTION DISTORTION CORRECTION
CIRCUIT (Side DPC Circuit) .............................. 85
1. DEFLECTION DISTORTION CORRECTION IC (TA8859P) .................................................... 86
2. SIDE DPC ............................................................................................................................................ 87
3. DIODE MODULATOR CIRCUIT ................................................................................................... 88
4. ACTUAL CIRCUIT ........................................................................................................................... 89
SECTION XIII
CLOSED CAPTION/EDS CIRCUIT ....................... 92
1. OUTLINE ............................................................................................................................................ 93
2. DATA TRANSMISSION FORMAT ................................................................................................ 93
3. DISPLAY FORMAT ........................................................................................................................... 94
4. CIRCUIT OPERATION .................................................................................................................... 95
SECTION XIV
POWER CIRCUIT ..................................................... 98
1. OUTLINE ............................................................................................................................................ 99
2. RECTIFYING CIRCUIT AND STANDBY POWER SUPPLY ................................................... 100
3. MAIN SUPPLY CIRCUIT............................................................................................................... 100
4. OUTLINE OF CURRENT RESONANT TYPE SUPPLY ........................................................... 101
5. FUNDAMENTAL THEORY ........................................................................................................... 101
6. ACTUAL CIRCUIT ......................................................................................................................... 102
7. OTHER POWER CIRCUIT ........................................................................................................... 105
8. PROTECTOR MODULE (Z801) .................................................................................................... 106
4
SECTION XV
DSP CIRCUIT .......................................................... 109
1. ORIGINS OF DOLBY SURROUND ............................................................................................. 110
2. THE DOLBY MP MATRIX ............................................................................................................ 110
3. THE DOLBY SURROUND DECODER ......................................................................................... 111
4. DSP CIRCUIT ................................................................................................................................... 111
5. DSP (Digital Surround Processor) IC ............................................................................................. 114
6. SURROUND CIRCUIT ................................................................................................................... 116
7. INPUT BALANCE CIRCUIT ......................................................................................................... 116
8. MATRIX CIRCUIT ......................................................................................................................... 117
9. FILTER CIRCUIT (ANTI-ALIAS FILTER)................................................................................. 117
10. DSP CIRCUIT (DELAY) ............................................................................................................... 118
11. 7 kHz LOW PASS FILTER ........................................................................................................... 119
12. DOLBY NR CIRCUIT ................................................................................................................... 120
13. DSP FRONT ADDITION CIRCUIT ............................................................................................ 121
14. BUS CONVERTER ........................................................................................................................ 122
15. NEUTRAL BIAS ............................................................................................................................ 122
16. AUDIO OUTPUT AMPLIFIER (For Rear SP) .......................................................................... 123
17. TROUBLESHOOTING CHART ................................................................................................. 124
SECTION XVI
FAILURE DIAGNOSIS PROCEDURES ............... 125
1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES........................................... 126
2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES ......................................... 127
3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT .............................. 128
4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES ........................... 129
5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE ............................................................. 130
6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES ......................................................................... 131
5
SECTION I
OUTLINE
6
1. OUTLINE OF N5SS CHASSIS 3. MAJOR SPECIFICATIONS (NEW
(CN32E90, CN35E90) FUNCTIONS IN ADDITION TO THOSE
OF N5SS)
The N5SS chassis is a complete bus control type
chassis where the deflection circuit is controlled by a newly (1) EOS (Extended-Data-Service)
developed I2C-bus line control system. (2) Center-Ch-Audio-Input provided
7
5. CONSTRUCTION OF CHASSIS
DPC circuit
CCD circuit
PIP circuit
SIGNAL circuit
EDS, RGB SW
circuit
IF/MTS/A-PRO
module
AUDIO OUT
CRT circuit
CONVERTER trans
A/V circuit
8
Fig. 1-1
RF SW
POWER/DEF circuit
V. OUT
DPC circuit
H.OUT
H.OUT trans
6. LOCATION OF CONTROLS
6-1. TV Set
For specific use of each control, consult the corresponding page numbers in brackets.
Front View
POWER indicator
POWER
POWER button
Remote sensor
Press to open
the door
VIDEO/AUDIO IN
jacks <VIDEO 3> CHANNEL buttons
Fig. 1-2
9
Rear view
EXTernal SPEAKER
terminals
VIDEO/AUDIO IN jacks
<VIDEO 1>
Fig. 1-3
10
6-2 Location of Controls (Remote Control)
Only the buttons that are used to operate the TV set are described here.
For details on the use of each control, refer to pages in brackets.
POWER button
TV/CABLE/VCR/AUX switch
Set to "TV" to control the TV.
MUTE button
TV/VIDEO
VOLUME buttons
RTN buttons
PIP function buttons
AUDio button
SET UP button
PICture button
OPTION button
RESET button EXIT button
ANT 1/2 button -\+ buttons
C.CAPT button FAV -/+ buttons
Fig. 1-4
11
6-3 Monitor Panel
5 3 9 4 7
TV Rear
TV Front
10 11 1 2 8 6
Fig. 1-5
, , VIDEO 1/VIDEO 2/VIDEO 3 IN Jacks — PIP AUDIO OUT Jacks — provide fixed-level
provide for direct connection of video devices audio outputs from whatever is displayed on the
(VCR, video disc player, camcorder, etc.) with PIP window screen.
video/audio outputs.
EXTERNAL SPEAKER Terminals — provide
, S-VIDEO IN Jacks —provide for direct S-video for direct connection of external speakers.
connection from an VCR or a video disc
player. The TV's VIDEO 1/3 audio jacks can MAIN SPEAKER Switch — lets you turn off
also be used to connect the VCR's audio cables. TV's built-in speakers so that sound will instead
come through speakers connected to
VIDEO/AUDIO OUT Jacks --- provide fixed- EXTERNAL SPEAKER terminals.
level audio and video outputs from whatever is
displayed on the screen. REAR SPEAKER Terminals — provide for
direct connection of the supplied Surround
VARIABLE AUDIO OUT Jacks --- feed Speakers.
volume-controlled stereo audio out from
whatever is displayed on the screen, allows
connection of audio amplifier and lets you adjust
sound level with TV's remote.
12
CRT DRIVE PCB
+27V
B 6 33 B SDA SCL Q302
HIGH VOLTAGE
27 28 13 Q370
7. CN32D90 BLOCK DIAGRAM
E/W CORRECTION
C 2SA933SQ
TA8859AP Q462 DPC
32 31 30 29 I2C-BUS LINE Q402 Q404 T461
2SC1740S-Q
KEY SDA SCL STOP SYNC H DRIVE H OTUTPUT
CONTROL QA01 MICROCOMPUTER 2SC1569FA-5 2SD2253(FA)
TMP87CS38N-3152 I 2C Bus line
-27V FBT
EDS/C.C
TB40 D840
5 6 D371
13
VIDEO SDA SCL KEY TFB
INPUT 3 ICA02 CONTROL CCD UNIT HEATER
MEMORY
4132AD
PB5419 4132BD
24LCO4BI/P V Y C F801 TB01
ST24C04CB6
DG DC DD T862
5A SR801 D801
Fig. 1-6
D883 F470 2A +125V
Q801 33V
V-AV D471
Z801
EA
L78MR05 D847 D885 F883 5A PROTECTOR
TRANS
EH +24.5V
Q840
CONVERTER
36 38
V L R Y R V 43 AB +12V
} PROTECTOR
POWER/DEF UNIT
STR-
2SC1B15Y
V SDA SCL C C 32 EI C-COMB
VIDEO 42 25 24 1 2 34 AJ QE06
INPUT 1 Q670 SW
OVER VOLTAGE
OVER HEAT
AUDIO OUT
VIDEO VAR-L
L 4 11
AI R883
OUTPUT Q862
R 2
AT VAR-R PHOTO-COUPLER
W 1 8 TLP621GR-L
TA8256H
12
9V-2 Q832
L R L R R L W
A/V PCB
40
PIP VAR 5V-3 Q831
AUDIO AUDIO
R L WOOFER
5V-2 Q830
8. [US, CANADA] SPECIFICATION FOR MODEL's 1995
CHASSIS C C C C C
MODEL Nbr CN27E90 CX32E70 CN32E90 CE35E15 CF35E50
DERIV
CRT
SPECIFICATION HITACHI TDD TDD *TDD *TDD
1 Picture Tube *FST-D/T NF-D/T NF-D/T *FST-D/T FST-D/T
* 2 Channel Capacity 181ch 181ch 181ch 181ch 181ch
G 3 C. Caption ● ● ● ● ●
E 4 MTS with dbx ● ● ● ● ●
N 5 Bass, Tre, Balance ● ● ● ● ●
E 6 Sub-Audio-Program ● ● ● ● ●
R
7 Remote band unit *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Unive (36k) *Unive (36k)
A
L 8 Picture-in-Picture ● (2TN) ● (2TN) ● (2TN) *● (1TN) ● (1TN)
9 LED Indicators (RED) ● (Power) ● (Power) ● (Power) *● (Power) ● (Power)
10 Local Keys 8key 8key 8key 8key 8key
11 Dolby Surround — — ● — —
12 Dig-Sound Processor — — ● (DSP4ch) — —
* 13 Front Surround ● ● — ● ●
S 14 Cyclone ABX ● — ● — —
O
15 Sub-Bass-System — ● — — —
U
N 16 Audio Output *10Wx2 & 13W 10Wx2 10Wx2 & 10Wx2 10Wx2
D 13W & 5Wx2
17 Speaker Size & Nbr *80x120x2 70x130x2 80x120x2 70x130x2 70x30x2
& 100R (Hon) 100R & REAR
18 Comb Filter *● (GLS) ● (CCD) ● (CCD) ● (CCD) ● (GLS)
* 19 Dy-Quadruple Focus — — — — —
P 20 Scan Velocity Modu ● ● ● ● ●
I
C 21 Vert Contour Corre ● ● ● ● ●
T 22 Black Level Expand ● ● ● ● ●
U 23 Flesh Tone Correct *● ● ● ● ●
R 24 Dynamic Noise Reduc *● ● ● ● ●
E 25 Picture Preference ● ● ● ● ●
26 Horiz Resolution 650 700 700 800 800
27 Parental-Ch Lock ● ● ● ● ●
* 28 Channel Label (32ch) ● ● ● ● ●
O
29 3-Language Display ● ● ● ● ●
T
H 30 Clock/Off-Timer *●/● ●/● ●/● ●/● ●/●
E 31 Favorite Channel *● *● *● *● *●
R 32 Extended-Data-Servi *● *● *● *● *●
33 Star-Sight-decoder — — — — —
34 S-Video In-Term ● (1+1) ● (1+1) ● (1+1) ● (1) ● (1)
* 35 Audio, Video-In/Out 1+2/— 1+2/1 1+2/1 *3/1 3/1
T 36 Front AV Jack *● ● ● — —
E 37 Variable Audio Out ● ● ● ● ●
R 38 2-RF Input ● ● ● — —
M
39 Ext Speaker Term ● ● ● ● ●
S
40 PIP Audio Out Jack — *— *● — —
41 Center-Ch-Aud-Input — *● *— — —
* 42 Speaker-Box -- — ● SS-SR94 — —
AC 43 Others — — — — —
*Cabinet NEW CX32D70 CN32D90 *CE35D10 CF35D50
PARTS SUPPLY (ISO) — — — — —
14
CHASSIS C C C C C
MODEL Nbr CX35E60 CX35E70 CX35E81 CN35E90 CN35E95
CONSOLE CINEMA
CRT
SPECIFICATION TDD TDD TDD TDD TDD
1 Picture Tube FST-D/T NF-D/T NF-D/T NF-D/T NF-D/T
* 2 Channel Capacity 181ch 181ch 181ch 181ch 181ch
G 3 C. Caption ● ● ● ● ●
E 4 MTS with dbx ● ● ● ● ●
N 5 Bass, Tre, Balance ● ● ● ● ●
E 6 Sub-Audio-Program ● ● ● ● *●
R
7 Remote band unit *A-Univ (42k) *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Intelig+EZ
A
L 8 Picture-in-Picture ● (2TN) ● (2TN) ● (2TN) ● (2TN) ● (2TN)
9 LED Indicators (RED) ● (Power) ● (Power) ● (Power) ● (Power) ● (Power)
10 Local Keys 8key 8key 8key *8key *8key
11 Dolby Surround — — — ● ●
12 Dig-Sound Processor — — — ● (DSP4ch) ● (DSP4ch)
* 13 Front Surround ● ● ● — —
S 14 Cyclone ABX — — — ● ●
O
15 Sub-Bass-System ● ● ● — —
U
N 16 Audio Output 10Wx2 10Wx2 10Wx2 10Wx2 10Wx2
D & 13W, 5Wx2 & 13W, 5Wx2
17 Speaker Size & Nbr 70x130x2 70x130x2 70x130x2 80x120x2 & 80x120x2 &
*100R, REAR *120R, REAR
18 Comb Filter ● (DIG) ● (DIG) ● (DIG) ● (DIG) ● (DIG)
* 19 Dy-Quadruple Focus ● ● ● ● ●
P 20 Scan Velocity Modu ● ● ● ● ●
I
C 21 Vert Contour Corre ● ● ● ● ●
T 22 Black Level Expand ● ● ● ● ●
U 23 Flesh Tone Correct ● ● ● ● ●
R 24 Dynamic Noise Reduc ● ● ● ● ●
E 25 Picture Preference ● ● ● ● ●
26 Horiz Resolution 800 800 800 800 800
27 Parental-Ch Lock ● ● ● ● ●
* 28 Channel Label (32ch) ● ● ● ● ●
O
29 3-Language Display ● ● ● ● ●
T
H 30 Clock/Off-Timer ●/● ●/● ●/● ●/● ●/●
E 31 Favorite Channel *● *● *● *● *●
R 32 Extended-Data-Servi *● *● *● *● *●
33 Star-Sight-decoder — — — — —
34 S-Video In-Term ● (1+1) ● (1+1) ● (1+1) ● (1+1) ● (1+1)
* 35 Audio, Video-In/Out 1+2/1 1+2/1 1+2/1 1+2/1 1+2/1
T 36 Front AV Jack ● ● ● ● ●
E 37 Variable Audio Out ● ● ● ● ●
R 38 2-RF Input ● ● ● ● ●
M
39 Ext Speaker Term ● ● ● ● ●
S
40 PIP Audio Out Jack — *— *— *● *●
41 Center-Ch-Aud-Input — *● *● *— *—
* 42 Speaker-Box — — — ● SS-SR94 ● SS-SR94
AC 43 Others — *VCR-Storate — *VCR-Stora
*Cabinet C35D60 CX35D70 NEW (DAX) CN35D90 NEW (BLK)
PARTS SUPPLY (ISO) — — — — —
15
SECTION II
TUNER, IF/MTS/S.PRO MODULE
16
1. CIRCUIT BLOCK
EL466L SIF
VIF/SIF output Sound
SAW
Tuner Multiplex S.PRO Circuit
Filter Circuit
Circuit
RF AGC
C-IN
R-IN L-IN
TP12 TV TV
Video output R-OUT L-OUT
C-OUT
R-OUT
To A/V switch circuit L-OUT
AFT output
(L+R)
-OUT
1-1. Outline
(1) RF signals sent from an antenna are converted into (5) VIF/SIF circuit uses PLL sync detection system to
intermediate frequency band signals (video: 45.75 MHz, improve performances shown below:
audio: 41.25 MHz) in the tuner. (Hereafter, these signals • Telop buzz in video over modulation
are called IF signals.) • DP, DG characteristics (video high-fidelity
(2) The IF signals are band-limited in passing through a reproduction)
SAW filter. • Cross color characteristic (coloring phenomenon at
(3) The IF signals band-limited are detected in the VIF color less high frequency signal objects)
circuit to develop video and AFT signals. (6) HIC SBX1637A-22 is used in the audio multiplexer
(4) The band-limited IF signals are detected in the SIF circuit to minimize the size with increased performance.
circuit and the detected output is demodulated by the (7) As a sound control processor, TA1217N is used. I2C-
audio multiplexer, developing R and L channel outputs. bus data control the DAC inside the IC to perform
These outputs are fed to the A/V switch circuit. switching of the audio multiplexer modes.
(5) A sound processor (S.PRO.) is provided.
17
2-2-2. Terminals (Tuner section)
2. TUNER
Name Function
2-1. Outline IF OUT IF outputs (P=45.75 MHz, C=42.17 MHz,
(1) Type name: EL466L S=41.25 MHz)
(2) Applicable 181CH
BM Tuner power supply (9V)
(3) I2C-bus version
(4) PLL-integrated RF AGC Gain control terminal to obtain constant
IF output
VT Control voltage to select channels
EL466L
PLL Selection
Tuner Section
2 5V C 1.4 20 7.8
9 VT FF 17.9 62 19.4
LL 24.2 69 23.6
Fig. 2-2 Tuner terminal layout
* VT voltage not indicated for a channel falls between
those values for channels just upper and lower the channel.
VHF 2~13CH
UHF 14~69CH 181CH in total
CATV A-6~, J~W, AA~BBB, 65~92, 100~127CH
18
3. IF/MTS/S.PRO MODULE 3-1-2 Video PIF Circuit
A PIF detector switching carrier is oscillating at a frequency
The IF/MTS/S.PRO module (MVUS34S) limits bandwidth adjusted to 45.75 MHz with L051 (VCO CW coil) under no
of IF signals and detects video and audio signals. The module RF signal input. When an RF signal enters, an IF video
consists of IF amplifiers, SAW (surface acoustic wave) carrier is fed to APC section from IF AMP inside the IC, and
filter, and PIF IC. The SAW filter has a wideband response the detector switching carrier is adjusted by the APC, VCO,
to improve picture quality and audio buzz characteristic and, etc. in the PLL circuit so that its frequency and phase are
develops separate outputs of video and audio signals. The matched to those of the IF video carrier to perform precise
PIF IC employs a PLL complete sync detection + audio split sync detection. Thus processed video output is developed at
carrier system. pin 21.
3-1. IF/MTS/S.PRO Module (MVUS34S) PLL lock speed is automatically controlled by adding the
3-1-1. Module Terminal Layout video signal at pin 21 to pin 1. That is, since the video signal
is not output at operations of power on, CH switching, etc.,
the APC filter between pin 16 and GND consists of C022 and
C053, and R018, and the filter effect decreases, thus increasing
PLL lock speed.
Next, when a video out exists, the internal resistance is short-
circuited and the APC filter consists of C022 and C053,
internal resistance, and R018. As a result, the filter effect
increases and the PLL lock speed decreases. Consequently,
under normal signal reception, phase of the detector switching
carrier is locked in a stable condition if an IF video carrier is
lost for a short time due to over modulation, etc. By combining
9 1
such a PLL complete sync detection system and a wideband
27 12
SAW filter shown in Fig. 2-4, a wideband (4.2 MHz) video
detection output with less beat interference will be obtained.
19
4.5MHz SIF SIGNAL
Z003
FM DET. COIL
L053
SIF BANDWIDTH
15 11 12
TO SOUND
14. R151
17. MPX IC
APC L051
S
Q002 SIF DET VCD VCO C106
18
CW COIL
23
Q003 L502
Z001 7
AFT COIL
SAW
IF AMP
FILTER 5 IF VIDEO
GAIN – 14dB 21
AMP DET.
F1802R 4 TP12
R021
22
LOCK
Z002
-6dB 1 Q004
CONTROL
AGC
2 13 16 20
-15dB
R022
R018
RF AGC C022
S C P
R051
41.25M 45.75M C053
VIDEO IF BANDWIDTH
1 2 3 4 5 6 7 8 9
GND IF-IN N.C +B(9V) RF AGC AFC VIDEO OUT ADR SW M
20
3-1-4. Audio Multiplex Demodulation Circuit Then, both are fed to the matrix circuit. At the same time,
The sound multiplex composite signal FM-detected in the each of the stereo pilot signal fH and the SAP pilot signal 5fH
PIF circuit enters pin 12 of HIC (hybrid IC) in passing is also demodulated to obtain an identification voltage. With
through the separation adjustment VR RV2 and amplified. the identification voltage thus obtained and the user control
After the amplification, the signal is split into two: one enters voltage are used to control the matrix.
a de-emphasis circuit, and only the main signal with the L- The audio signals obtained by demodulating the sound
R signal and a SAP signal removed enters the matrix circuit. multiplex signal develop at pin 10 and 11 of HIC and develop
At the same time, the other passes through various filters and the terminals of 12 and 14 of the module.
trap circuits, and the L-R signal is AM-demodulated, and the
SAP is FM-demodulated.
MVUS32S
To AV select circuit
21
3-1-5. A.PRO Section (Audio Processor) All these processing are carried out according to the BUS
The S.PRO section has following functions. signals sent from a microcomputer.
(1) Woofer processing (L+R output)
(2) High band, low band, balance control Fig. 2-6 shows a block diagram of the A.PRO IC.
(3) Sound volume control, cyclone level control
(4) Cyclone ON/OFF
TA1217N
1 27 29 22 32 33 30 9 8 28
Lin 30 26 Lout
BALANCE
TONE CONTROL
Rin 34 25 Rout
2 Center
Cin LEVEL VOLUME
18 Cout
10 Wout
Win Woofer 17
3 LPF
LEVEL
16
15
I/O
14
SDA 20 13
2
I C D/A
12 SAP det.
CONV
SGL 21 11 STE det.
4 5 6 7 31 24 23 22 19
16 17 18 19 20 21 22 23 24 25 26 27
22
4. PIP TUNER
Lable
Name
Lot No.
TUNER SAW VIF/SIF
SECTION FILTER CIRCUIT
RF AGC
1 15
AFT VIDEO AUDIO
OUTPUT OUTPUT OUTPUT
Fig. 2-7
Terminal No. Name
1 NC
4-1. Outline 2 32V
The PIP tuner (EL922L) consists of a tuner and an IF block 3 S-CLOCK
integrated into one unit. The tuner receives RF signals 4 S-DATA
induced on an antenna and develops an AFT output, video 5 NC
output, and audio output. 6 ADDRESS
The tuner has receive channels of 181 as in the tuner for the
7 5V
main screen and it is also controlled through the I2C-bus.
As the IC for the IF, a PLL complete sync detection plus 8 RF AGC
audio inter carrier system are employed. 9 9V
10 AUDIO
11 GND
12 AFT
13 NC
14 GND
15 VIDEO
23
SECTION III
CHANNEL SELECTION CIRCUIT
24
1. OUTLINE OF CHANNEL SELECTION • Setting of memory values for video parameters
CIRCUIT SYSTEM such as white balance (RGB cutoff, GB drive) and
gcorrection, etc.
The channel selection circuit in the N5SS chassis employs • Setting of video parameters of video modes
a bus system which performs a central control by connecting (Standard, Movie, Memory)
a channel selection microcomputer to a control IC in each
circuit block through control lines called a bus. In the bus (3) CONTROL OF A/V SWITCH IC (QV01 Toshiba
system which controls each IC, the I2C bus system (two line TA1219N)
bus system) developed by Philips Co. Ltd. in the Netherlands • Preforms source switching for main screen and
has been employed. sub screen
The ICs controlled by the I2C bus system are : IC for audio • Performs source switching for TV and three video
signal processing (QN06), IC for V/C/D signal processing inputs
(Q501), IC for A/V switching (QV01), IC for non volatile
memory (QA02), Main and sub U/V tuners (H001, HY01), (4) CONTROL OF NON-VOLATILE MEMORY IC
IC for deflection distortion correction (Q302), IC for PIP (QA02 Microchip 24LC04BI/P)
signal processing (QY04), IC for DSP (QM01), IC for • Memorizes data for video and audio signal
closed caption control (Q701). adjustment values, volume and woofer adjustment
values, external input status, etc.
Differences from N4SS chassis are as follows; • Memorizes adjustment data for white balance
1. On-screen function inside microcomputer is used. (RGB cutoff, GB drive), sub-brightness, sub color,
Separate IC is not used for on-screen. sub tint, etc.
2. The microcomputer does not have the closed caption • Memorizes deflection distortion correction value
function, but controls separate IC for closed caption. data adjusted for each unit.
3. The system uses two channels of I2C bus. One is only
for non-volatile memory. (5) CONTROL OF U/V TUNER UNIT (H001 Matsushita
EL466L, HY01 Toshiba EL922L)
2. OPERATION OF CHANNEL • A desired channel can be tuned by transferring a
SELECTION CIRCUIT channel selection frequency data (divided ratio
data) to the I2C bus type frequency synthesizer
equipped in the tuner, and by setting a band switch
Toshiba made 8 bit microcomputer TLCS-870 series for TV
data which selects the UHF or VHF band.
receiver, TMP87CS38N-3152 is employed for QA01.
With this microcomputer, each IC and circuit shown below
(6) CONTROL OF DEFLECTION DISTORTION
are controlled.
CORRECTION IC (Q302 Toshiba TA8859P)
• Sets adjustment memory value for vertical
(1) CONTROL OF AUDIO SIGNAL PROCESS IC (QN06
amplitude, linearity, horizontal amplitude,
Toshiba TA1217N)
parabola, corner, trapezoid distortion.
• Adjustments for volume, treble, bass and balance
• Selection between surround mode and DSP mode,
(7) CONTROL OF PIP SIGNAL PROCESS IC (QY04
and level adjustment
Toshiba TC9083F)
• Level adjustment of BAZOOKA system
• Controls ON/OFF and position shift of PIP.
• Audio muting during channel selection or no signal
reception.
(8) CONTROL OF DIGITAL SOUND PROCESSOR IC
(QM04 Yamaha YSS238-D)
(2) CONTROL OF VIDEO/CHROMA/DEF SIGNAL
• Performs mode switching of DSP.
PROCESS IC (Q501 Toshiba TA1222N)
• Adjustments for uni-color, brightness, tint, color
(9) CONTROL OF CLOSED CAPTION/EDS (QM01
gain, sharpness and PIP uni-color
Motorola XC144144P)
• Setting of adjustment memory values for sub-
• Controls Closed Caption/EDS.
brightness, sub-color and sub-tint, etc.
25
3. MICROCOMPUTER
Microcomputer TMP87CS38N-3152 has 60k byte of ROM IIC device controls through I2C bus. (Timing chart : See fig.
capacity and equipped with OSD function inside. 3-1)
The specification is as follow. • LED uses big current port for output only.
• Type name : TMP87CS38N-3152 • For clock oscillation, 8MHz ceramic oscillator is used.
• ROM : 60k byte • I2C has two channels. One is for EPROM only.
• RAM : 2k byte • Self diagnosis function which utilizes ACK function of
• Processing speed : 0.5m s (at 8MHz with Shortest I2C is equipped
command) • Function indication is added to service mode.
• Package : 42 pin shrink DIP • Remote control operation is equipped, and the control
• I2C-BUS : two channels by set no touch is possible. (Bus connector in the
• PWM : 14 bit x 1, 7 bit x 9 conventional bus chassis is deleted.)
• ADC : 8 bit x 6 (Successive comparison system, • Substantial self diagnosis function
Conversion time 20ms) (1) B/W composite video signal generating function
• OSD (micom inside, green crossbar added)
Character kinds : 256 (2) Generating function of audio signal equivalent
Character display : 24 characters x 12 lines to 1kHz (micom inside)
Character dot : 14 x 18 dots (3) Detecting function of power protection circuit
Character size : 3 kinds (Selected by line) operation
Character color : 8 colors (Selected by character) (4) Detecting function of abnormality in IIC bus
Display position : Horizontal 128 steps, Vertical line
256 steps (5) Functions of LED blink indication and OSD
This microcomputer performs functions of AD converter, indication
reception of U/V TV and OSD display in one chip. (6) Block diagnosis function which uses new VCD
and AV SW
SDA
Fig. 3-1
26
4. MICROCOMPUTER TERMINAL FUNCTION
TMP87CS38N3152 (QA01)
Fig. 3-2
27
<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >>
No. Terminal Name Function In/Out Logic Remarks
1 GND 0V
2 BAL INPUT BALANCE Out PWM out
3 REM OUT REMOTE CONTROL Out Remote control output
SIGNAL OUT
4 MUTE SOUND MUTE OUT Out Sound mute output
5 SP MUTE SPEAKER MUTE Out In muting = H
6 DEF POW Out
7 POWER POWER ON/OFF OUT Out Power control In ON=H
8 LED POWER LED OUTPUT Out Power LED on-control
LED lighting=L
9 POWER LNB Out 0V
10 LNB DET In 0V
11 SCL() IIC BUS CLOCK OUT Out IIC bus clock output 0
12 SDA() IIC BUS DATA IN/OUT In/Out IIC bus data input/output 0
13 SYNC VCD H SYNC INPUT In Main picture H. sync signal input
14
15 AFT2 IN In Sub tuner AFT S-curve input
16 AFT1 UV MAIN S-CURVE In Main tuner AFT S-curve
SIGNAL signal input
17 KEY A LOCAL KEY INPUT In Local key detection: 0 to 5V
18 KEY B LOCAL KEY INPUT In Local key detection: 0 to 5V
19 SGV TEST SIGNAL OUT Out Test signal output In normal=L 0V
20 SGA TEST AUDIO OUT Out Test audio output In normal=L 0V
21 VSS POWER GROUNDING — 0V: Gounding voltage 0V
22 R R Out At display on:Pulse
23 G G Out At dispaly on:Pulse
24 B B Out At dispaly on:Pulse
25 Y/BL BL Out At dispaly on:Pulse
26 HSYNC In HSYNC for OSD display Pulse
27 VSYNC In VSYNC for OSD display Pulse
28 OSC1 DISPLAY CLOCK Out 4.5MHz Pulse
29 OSC2 DISPLAY CLOCK In Pulse
30 TEST TEST MODE In GND fixed 0V
31 XIN SYSTEM CLOCK In System clock input 8MHz pulse
32 XOUT SYSTEM CLOCK Out System clock output 8MHz 8MHz pulse
33 RESET SYSTEM RESET In System reset input (In reset=L) 5V
34 SW IN
35 RMT IN REMOTE CONTROL IN In remote control pulse input=L In reception of
SIGNAL INPUT remote pulse
36 SYNC AV1 HSYNC INPUT In External H. sync signal input Pulse
37 SCL1 IIC BUS CLOCK OUT Out IIC bus clock output 1 Pulse
38 SDA1 IIC BUS DATA IN/OUT In/Out IIC bus data input/output 1 Pulse
39 GND 0V
40 NC
41 ACP NSYNC INPUT In AC pulse input
42 VDD POWER — 5V 5V
28
5. EEPROM (QA02)
EEPROM (Non volatile memory) has function which, in spite of power-off, memorizes the such condition as channel selecting
data, last memory status, user control and digital processor data. The capacity of EEPROM is 8k bits. Type name is 24LC04BI/
P or ST24C04CB6, and those are the same in pin allocation and function, and are exchangeable each other. This IC controls
through I2C bus. The power supply of EEPROM and MICOM is common. Pin function of EEPROM is shown in Figure 3-3.
EEPROM(QA02)
A0 1 8 Vcc + 5V
Device adress
A1 2 7 NC
GND
A2 3 6 SCL
I2C-BUS line
Vss 4 5 SDA
Fig. 3-3
6. ON SCREEN FUNCTION
ON SCREEN FUNCTION indicates data like channel, volume. Formerly, exclusive use of OSD IC was used, but in N5SS,
OSD function is involved in microcomputer. Pin function concerning on-screen is shown in figure 3-4. Oscillation clock of OSD
is approx. 4.5MHz. 9MHz which becomes twice in microcomputer is dot clock. For oscillation coil, TRF1160D (LA02) is used.
QA01
B O 24 BOUT
R O 22 ROUT
VG
Fig. 3-4
29
7. SYSTEM BLOCK DIAGRAM
QA01
TMP87CS38N-3152
QA02 SDA 1 38
SCL 1 37 H001
MEMORY
24LC04B1/P
MAIN U/V TUNER
SDA SCL RMT 35 REMOTE
EL446L
SENSOR
5 6 UNIT SDA SCL
11 SCL 0
12 SDA 0 HY01
MAIN SCREEN
SDA SCL
PIP CONTROL
DATA CLK
6 5
Fig. 3-5
30
8. LOCAL KEY DETECTION METHOD
S15-2 S16-2
The circuit diagram shown left is the local key circuit. As can
be seen from the diagram, when
one of key among SA-01 to SA-08 is pressed, each of two
S15-3 S16-3 input terminal (pins 17, 18) developes
a voltage Vin corresponding to the key pressed. (The voltage
measurement and key identification
S15-4 S16-4 are carried out by an A/D converter inside the microcomputer
and the software.
S15-5 S16-5
S15-6 S16-6
S15-7 S16-7
31
9. REMOTE CONTROL CODE ASSIGNMENT
32
Custom codes are 40-BFH Custom codes are 40-BFH
Applicable
Code Applicable Conti- Code Applicable Conti-
Function to remote Function
control to TV set nuty to TV set nuty
33
Custom codes are 40-BFH
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH HORIZONTAL WIDTH (WID/PARA)
EBH TRAPEZOIDE CORRECTION (TRAP)
ECH TEST TONE
EDH DOLBY
EEH 3 DIMENTIONAL Y/C SEPARATION
EFH DPC
E0H STANDARD (HEIGHT LINEARITY) (VLIN/HIT)
E1H WIDE (HEIGHT LINEARITY) (VLIN)
F2H SCROOL
F3H WIDE 1, 2, 3
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
34
10. ENTERING TO SERVICE MODE 12. SERVICE ADJUSTMENT
1. PROCEDURE 1. ADJUSTMENT MENU INDICATION ON/OFF :
(1) Press once MUTE key of remote hand unit to MENU key ( on TV set)
indicate MUTE on screen. 2. During display of adjustment menu, the followings are
(2) Press again MUTE key of remote hand unit to keep effective.
pressing until the next procedure. a) Selection of adjustment item :
(3) In the status of above (2), wait for disappearing of POS UP/DN key (on TV/remote unit)
indication on screen. b) Adjustment of each item :
(4) In the status of above (3), press MENU (Channel VOL UP/ DN key (on TV / remote unit)
setting) key on TV set. c) Direct selection of adjustment item
R CUTOFF : 1 POS (remote unit)
2. Service mode is not memorized as the last-memory. G CUTOFF : 2 POS (remote unit)
3. During service mode, indication S is displayed at upper B CUTOFF : 3 POS (remote unit)
right corner on screen. d) Data setting for PC unit adjustment
SUB CONTRAST : 4 POS (remote unit)
11. TEST SIGNAL SELECTION SUB COLOR : 5 POS (remote unit)
SUB TINT : 6 POS (remote unit)
1. In OFF state of test signal, SGA terminal (Pin 20) and e) Horizontal line ON/OFF : VIDEO (TV)
SGV terminal (Pin 21) are kept “L” condition. f) Test signal selection : VIDEO (remote unit)
2. The function of VIDEO test signal selection is cyclically * In service mode, serviceable items are limited.
changed with VIDEO key (remote unit).
3. Test audio signal ON / OFF : 8 POS (remote unit)
Test Signal No. Name of Pattern * Test audio signal : 1kHz
0 Signal OFF
1 All black signal + R single color (OSD) 4. Self check display : 9 POS (remote unit)
2 All black signal + G single color (OSD) * Cyclic display (including ON/OFF)
3 All black signal + B single color (OSD)
4 All black signal 5. Initialization of memory :
5 All white signal CALL (remote unit) + POS UP (TV)
6 W/B 6. Initialization of self check data :
7 Black cross bar CALL (remote unit) + POS DN (TV)
8 White cross bar 7. BUS OFF :
9 Black cross hatch CALL (remote unit) + VOL UP (TV)
10 White cross hatch
11 White cross dot
12 Black cross dot
13 H signal (bright area)
14 H signal (dark area)
15 Black cross + G
35
13. FAILURE DIAGNOSIS PROCEDURE
Model of N5SS chassis is equipped with self diagnosis function inside for trouble shooting.
1. CONTENTS TO BE CONFIRMED BY CUSTOMER
(PROCEDURE)
(1) Set to service mode.
(2) Pressing “9” key on remote unit displays self diagnosis result on screen.
Every pressing changes mode as below.
SERVICE mode SELF DIAGNOSIS mode
36
4. UNDERSTANDING SELF DIAGNOSIS INDICATION
In case that phenomenon always arises. See figure 3-4 .
[CAUTION] White
All ways keep the following caution, in the state of Yellow
service mode screen. Cyan
Green
• Do not press “CHANNEL UP” button. This will cause
Magenta
initialization of memory IC. (Replacement of memory IC is Red
required. Blue
• Do not initialize self diagnosis result. This will change user
( COLOR BAR SIGNAL)
adjusting contents to factory setting value. ( Adjustment is
Color elements are positioned in sequence of high brightness.
required.)
37
14. TROUBLE SHOOTING CHART
(1) TV DOES NOT TURNED ON
YES
Relay sound
NO
NG
Check of voltage at pin 7 of QA01
(DC 5V).
OK
Check power circuit.
NG
8MHz oscillation waveform
at pin 32 of QA01.
OK
Check OSC circuit.
Replace QA01.
NG
Pulse output at pins 37 and 38 of QA01.
OK
NG
Voltage check at pin 32 of QA01
(DC 5V)
38
(2) NO ACCEPTION OF KEY-IN
Key on TV
OK
Check key-in circuit.
Replace QA01.
OK
No picture
NG
Voltage at pins of +5V, and 32V.
OK
39
(4) MEMORY CIRCUIT CHECK
NG
Voltage check at pin 8 of QA02 (5V).
NG
Pulse input at pins 5 and 6 of QA02
in memorizing operation.
OK
Check QA01.
Replace QA02.
No indication on screen.
NG
Check of character signal at pin 23
of QA01. (5VP-P )
OK
Check V/C/D circuit.
OK
Check OSC circuit.
OK
Check sync circuit.
Replace QA01.
40
SECTION IV
AUDIO OUTPUT CIRCUIT
41
1. OUTLINE
A/V PCB
VIF+MTS+S.PRO
MODULE ICV01 FOR PIP
IF MODULE
R 12 EQ 6 R L 29
MOTHER CHILD
TV TV R 31 AUDIO
L 14 ER 7 L
L 2 L PIP OUT
R L
VIDEO 1 11 L R 1 R (AUDIO)
VIDEO 1
13 R
R L
VIDEO 2 3 L VIDEO
VIDEO 2
9 R OUTPUT
TERMINAL VIF+MTS+A.PRO Q670
R L MODULE
VIDEO 3 15 L R
(FRONT INPUT) VIDEO 3 R out 25 2 12
17 R R
R 35 AS DSP 16 R L
L out 24 4 2
CIRCUIT
L 37 AR 18 L W
W out 22 1 11 L
PIP W
OUTPUT
R L
VARIABLE
AUDIO OUTPUT AI
TERMINAL
AJ
Fig. 4-1
42
2. AUDIO OUT IC
2-1. OUTLINE
In the model, CN32E90, the main amplifiers and woofer
output amplifiers use bipolar IC TA8256H and develop out
powers of 10W x 2+13W.
Vcc
25.5V
47mF
6 9
1mF RIPPLE FILTER Vcc
4k
L 4 OUTPUT-2 470mF
L AMP-2 8
30k
2.2W
RL (L)
350W 0.12mF
3 POW 10
PRE
GND GND
0.12mF
47mF 350W RL (R)
2.2W
(R)
1mF AMP-3 12
OUTPUT-3 470mF
R 2
R 4k
30k 5 (mute)
MUTING
(mute Tc)
7
30k
1mF 4k
W 1 OUTPUT-3 1000mF
W AMP-1 11
350W
(S) or (W) 2.2W
RL (W)
0.12mF
20kW
Fig. 4-2
43
SECTION V
A/V SWITCHING CIRCUIT
44
1. OUTLINE
2. IN / OUT TERMINALS
3. CIRCUIT OPERATION
45
AV SW CIRCUIT
TUNR/IMA TIF
L/R V out V Aout
EQ DSP
QV01 TA1218N
L/R in
18 C in
QA01
17 R in SYNC OUT 26 SYNC in
VIDEO 3
16 S in
15 L in PIP TV in 28
14 C in PIP L in 29 COMB
FILTER
13 R in Y in 30 Y out
VIDEO 1
12 S in PIP R in 31 V in
11 L in C in 32 C out
10 V in
9 R in C out 34 C in
VIDEO 2
R out 35 Q501
8 L in
7 V in Y out 36 Y in
6 R in L out 37
5 L in H out 38
2 PIP R out
PIP AUDIO PIP
OUT
1 PIP L out PIP V out 42 V in
MONITOR
OUT
Fig. 5-1
46
SECTION VI
VIDEO PROCESSING CIRCUIT
47
1. OUTLINE signals, and is converted to original color signal (R,G,B)
by RGB matrix. Next the signal is superimposed with
This circuit converts and amplifies video signal (Luminance OSD signal to be output to pins 41, 42 and 43, and is
and chroma signals) separated into Y/C, to original color supplied to CRT Drive circuit.
signal, and is supplied to CRT Drive circuit. (4) The signal for Scan Modulation is processed with
differential in Q501 to be output to pin 48 Besides, at
2. SIGNAL FLOW terminal for adjustment TP501, luminance and chroma
signals are automatically output according to the selected
Signal flow chart is shown in fig. 6-2 Block diagram. items of service mode.
(1) Luminance signal is input to pin 15 of Q501, and enters
into delayline inside Q501 to be output to pin 4. 3. CIRCUIT OPERATION
(2) Chroma signal is input to pin 13, and I/Q signal which All processing operation of video signal are done inside
is demodulated in color, is output to pins 5 and 6, and Q501. The outline of Q501 (TA1222N) is explained in the
next supplied to pins 51 and 52. next section. Here, major terminals excepting input/output
(3) The signal is processed on luminance and chroma terminals of Q501 are described.
48
Terminals concerning Video / Chroma circuit of Q501 are explained here.
#1 CW OUTPUT 3.58MHz which is synchronized to burst signal is output, and is used for clock of comb filter.
#2 SCP OUTPUT The signal which is superimposed with burst gate pulse and blanking pulse is output. It is not
used in this time.
#3 SECAM CONTROL When receiving SECAM (Color system of East Europe) signal, it produces DC output. It is not
used in this time.
#4 Y1 OUTPUT Luminance signal of Y1 input (# 15) is output through delay line.
#5 Q OUTPUT Chroma signal of #13 is demodulated in IQ, and Q signal is output.
#6 I OUTPUT I signal of those of IQ demodulated is output.
#7 1H DL CONTROL Color demodulation control signal of PAL, SECAM system (European color system) is output.
It is not used in this time.
#8 XTAL 3 Crystal oscillator terminal. Not used.
#9 XTAL 2 Ditto
# 10 XTAL 1 3.58MHz crystal oscillation terminal.
# 11 APC FILTER Color sync. phase detecting terminal.
# 12 Vcc 1 5V source (chroma line) terminal
# 13 C INPUT Color signal input terminal
# 14 GND Grounding terminal of chroma circuit
# 15 Y1 INPUT Luminance signal input terminal
# 32 PIP Ys Input terminal for switching pulse signal of PIP signal
# 33 PIP B Input terminal of PIP RGB signal
# 34 PIP G Ditto
# 35 PIP R Ditto
# 36 OSD Ys Input terminal for switching pulse signal of OSD signal
# 37 OSD B Input terminal for OSD RGB signal
# 38 OSD G Ditto
# 39 OSD R Ditto
# 40 Vcc 2 +9V source terminal
# 41 B OUTPUT RGB output terminal
# 42 G OUTPUT Ditto
# 43 R OUTPUT Ditto
# 44 GND Ground terminal of Y, color difference, RGB circuits
# 45 ABL Input terminal for ABL control
# 46 Vcc 3 +9V source terminal
# 47 Ym Input terminal for half tone control pulse which is supplied from
microcomputer
# 48 VSM Output terminal of velocity modulation signal
# 49 APL DET Detects average level of video signal for correcting DC transmission
# 50 BLACK DET Detects black area in video signal for black expanding circuit
# 51 I INPUT Input signal for I signal of IQ demodulation signal
# 52 Q INPUT Input signal for Q signal of IQ demodulation signal
# 53 Y2 INPUT Input terminal for Y-picture control circuit
# 54 COL Terminal for peak hold of color limiter
# 55 DAC 1 Test point (TP501) output terminal
# 56 DAC 2 External circuit control terminal (Not used)
49
0.6V(P)
TO COMB
CW OUTPUT DAC 2 (2bit)
56
COLOR IDENT. OUTPUT
1
DAC 1 (1bit)
SCP OUTPUT MONITOR OUTPUT
55
2
SECAM CONTROL COLOR LIMITER
54
3
1V(P-P)
Y1 OUTPUT Y2 INPUT
53
4
1V(P) 300mV
Q OUTPUT Q INPUT
52
5
I OUTPUT I INPUT
(P)
51
6
1H DL CONTROL BLACK PEAK HOLD
50
7
XTAL 3 APL DET.
4.43
or
49
N
8
XTAL 2 VSM OUTPUT
48
M
9
XTAL 1 Ym INPUT
3.58
10
47
POWER OFF INPUT
APC FILTER Vcc 3
11
46
Vcc 1 (+5V) ABL INPUT
12
45
300mV(P)
Y, COLOR DIFFERENCE,
CHROMA INPUT
13
RGB GND
44
CHROMA GND R OUTPUT
14
43
1V(P)
Y1 INPUT G OUTPUT
2.5V(P)(typ)
2.8V(P)(typ)
15
42
V. SEP. B OUTPUT
16
41
Vcc 2 (+9V)
1V(P)
SYNC INPUT
17
39
DEF GND
0.5V(P)(typ)
from OSD mCom
G ANALOG OSD INPUT
or R
pull
19
38
37
36
35
+B
H. OUT G INPUT
23
34
33
32
7.5V
1.0V(DIR)
7.5V(AFC)
31
8H
HD OUTPUT
SDA EXTERNAL BPP INPUT
27
30
1yb
29
<SDA>
<SCL>
peak to peak.
V(P) denotes value of
<5V
50
5 6 4 53 52 51 48
Q I Y Y I/Q VM VELOCITY
MODULATION
51
Sync
17
SYNC/DEF
PROCESSING
OSD
R G B Ys Ym
23 31 55 39 38 37 36 47
Q501 V/C/D
H.OUT VP
Microcomputer OSD
or EDS or C.C
SECTION VII
V/C/D/IC
52
1. OUTLINE
This IC enables more precise picture setting than that of former IC (TA8845N) by means of large scale employment
of IIC bus, and reduces many peripheral components by containing filters inside.
The main features (comparing TA8845) are as follows.
5. LOW COST OF IC
* Involving peripheral components inside ——> Down sizing of chip ——> Newly employment (NPN Tr area
ratio to former : -25%) of miniature process (PLAS-1 S process)
* Involving peripheral components inside——>Increasing of power consumption——>2 power supply system
(5V / 9V used)
* Involving peripheral components inside ——> Reducing of number of elements ——> Employment of new
circuit
(1) Reducing of gate (change of preset method) of register for IIC decoder
(2) Reducing of DAC elements (employment of rudder type DAC + temperature compensation circuit)
(3) Deletion of chroma CW, ACC (employment of 90 degree shift phase circuit with automatic adjustment)
53
VCD BLOCK DIAGRAM (TA1222N)
CORRECTION
BLK/AFC IN
BENDING
3'5" VCD
SYNC IN
Daf vCC
H. out
AFC1
17 20 21 25 24 19 22 23
GND (DEF) VCC (DEF)
H. V. PHASE DET PHASE DET H. PHASE H. DUTY
32 FM VCO H. BLK H. DRIVE
SYNC SEP <APC-1> <APC-2> SHIFT SW
H. H. Y.
V. Sep 16 V. SEP Y.P OUT 31 VER OUT
COUNT DOWN PARABOLA COUNT DOWN
V. SYNC
18 SYNC OUT
SYNC SEP OUT
27 SDA
SYNC CHIP DELAY D/A I2C BUS
Y IN 15 FDC TRAP SW REGISTER 26 GND
CLAMP LINE CONVERTER DECODER
19 SCL
BPF DELAY LINE DELAY LINE S W 4 Y1 OUT
CHROMA IN 13 SW TOK
29 GND
GND
GAMMA BLACK BLACK
GND 34 ACC AMP TOF SW Y. CLAMP 53 Y2 OUT
CORRECTION LEVEL COR. STRETON
VCC
9V 12
SUB B.C BLACK WHITE
(88) ACC DET A.P.L DET 30 BLACK PEAK
COLOR RESTORE PEAK DET PEAK DET HOLD
39 APL DET
P/N IDENT CHROMA SHARPNESS
APC FILTER 11 APC DET HPF TM AMP VM MUTE 28 VM OUT
BET BLK S DELAY LINE
R
T
X tal-1 CHROMA CW CHROMA SHARPNESS
10 T. NR AMP SUB CONT UNI COLOR
(3.58MHz) VCO MATRIX DEMOD. CONTROL
VCC 26
X tal-2 (PAL) 9 (98)
FILTER LPH 5 Q OUT
WPS HALF TONE CLAMP
AUTO ADJ FSC TRAP
X tal-3 (PAL) 8 6 Y OUT
I IN 51 33 B IN
35 R IN
UNI COLOR DELAY YS SW
COLOR TINF 36 OSD Ys IN
TIME
37 OSD B IN
AXIS HALF
CLAMP CLAMP OSD AMP 38 OSD G IN
G-Y MATRIX TONE
39 OSD R IN
COLOR COLOR
COLOR LIMITER 54 CDE YS SW 22 Ys IN
PEAK DET GAMMA
DAC 2 55
HI BRIGHT RGB PEAK
SW ABCL AMP 25 ABL IN
COLOR MATRIX ACL DET
DAC 2 56
B OUT
R OUT
G OUT
YM IN
HD OUT/BLACK
(SAND CASTLE)
CW OUT/
(FOR PAL)
SCP OUT
54
SECTION VIII
PIP MODULE
55
PMUS 02H (SN:23148232)
B-Y OFFSET
R-Y OFFSET
TINT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2 - NC 10 I GND
350µS
3 I GND 11 I VD 4.2V
0V
4.8V
4 O R OUT 4.1V 12 I HD 1µS
10µS 4.2V
4.8V 3.0V 6V
5 O G OUT 4.1V 13 I/O SCL Or
-0.9V 0V
4.8V
6 O B OUT 4.1V 14 I/O SCL B CHASSIS C CHASSIS
7 I GND 15 - NC
4.8V
8 I PIP VIDEO 2.8V
56
PMUS02H
<BLOCK DIAGRAM OF PIP MODULE>
RY55 RY54
WAVE FORM
HD 10 78 HDCN HDPN18
57
MODULATION
76 VDCN VDPN16
VD 11
QY03 QY01
QY01
TC9083F mPC1832GT
mPC 1832GT
(PIP PROCESSOR) (PIP V/C/D)
(PIP V/C/D)
VD
11
HD
12
SECTION IX
SYNC SEPARATION, H-AFC,
H-OSCILLATOR CIRCUITS
58
1. SYNC SEPARATION CIRCUIT
V SYNC WAVEFORM
V sync signal
SEPARATION SHAPEING
(Reset pulse)
CIRCUIT CIRCUIT
Pedestal Level
D
B
B
A
Sync Separation Level A:B=C:D
b: Small Amplitude Sync. Signal
a: Corect Sync. Signal
59
1-1-2. V Sync Separation Circuit First, phases of a 32 fH counted-down signal and a H sync
To separate a V sync signal from the composite sync signal signal contained in broadcasting signal are compared in the
consisting of V and H sync signals mixed, two stages of AFCI loop and the loop develops an H pulse signal for the
integration circuits are provided inside the IC. The circuit AFCII loop. That is, when a phase deference 01 exists in
consists of a differential circuit and a Miller integration comparison of the phase of fH signal developed by counting
circuit, and has following functions. down the 32 fH signal and the phase of H sync signal of the
(1) Removes H sync signal component. broadcasting signal, an error signal corresponding to the
(2) Maintain stable V sync performance for a tape recorded phase different is detected and a correction voltage ???1
with a copy guard. corresponding to the error output is generated. With this
(3) Stabilized V sync performance under special field correction voltage, the 32 fH oscillator circuit is controlled.
conditions (poor field, ghost, sync depressed, adjacent The correction (control) voltage for the oscillator varies in
channel best). direction of positive or negative corresponding to phase lead
The V sync signal separated in this stage is processed in a or lag of the fH pulse (developed by counting down) from the
waveform shape circuit and then used as a reset pulse in the H sync signal. As the H oscillator (32 x fH), a voltage
V division circuit as stated later. controlled oscillator (VCO), oscillation frequency and phase
of which can be controlled with the control voltage is used.
2. H AFC (Automatic Frequency Control) Next, an H pulse signal is created from the fH signal counted
CIRCUIT down, and the pulse is used instead of the H sync signal in the
AFCII circuit. The AFCII circuit differs in the loop of the
A sync system which performs synchronization with each count down circuit and H output circuit.
waveform of the sync signal as performed in a sync system The AFCII circuit compares phase of a H BLK pulse created
in the V circuit is called a direct type sync system. However, by waveform shaping a AFC pulse from the FBT and a phase
if the synchronization for the H oscillator is carried out with of the H pulse, and detects an error component corresponding
this method, the H oscillator synchronizes with external to the phase difference 02 (if exist) and develops a
noises and the H synchronization will be disturbed. To correction voltage V2 corresponding to the error, thereby
prevent this, an output of the H oscillator is compared with controlling the phase of Q501 H out.
a reference H sync signal to detect deviations of frequency The H output control voltage varies in a positive or negative
and phase. The H oscillator is automatically controlled with direction corresponding to the phase lead or lag of the H BLK
the detected output averaged. This circuit is called an AFC pulse from that of the H pulse. The phase of H out is varied
circuit. with the control voltage to make synchronization with the H
In the N4SS chassis, a conventional AFC circuit is not pulse phase.
employed but a new double AFC circuit built-in the TA1222N The purpose of the double AFC circuit employed this time is
is used. Fig. 9-3 shows the AFC circuit and the block diagram to improve horizontal jitter under signal reception in a poor
of the circuit. electrical field. The jitter in the poor field strength and
AFC II LOOP
H DRIVE
H COUNT DOWN PHASE DETECTION
H OUTPUT
(DIVIDING) CIRCUIT
CIRCUIT
AFC I LOOP
FBT PULSE
(AFC PULSE)
60
distortion due to phase difference are incompatible. That
is,to improve the jitter under poor field strength, response
speed must be slowed by lowering the AFC sensitivity. On
the other hand, to improve distortion due to the phase
difference, the response must be increased by increasing the
AFC sensitivity.
H Vcc
In a conventional AFC circuit, setting of the sensitivity is
carried out at one part only, so an compromise point for both
characteristics must be found. However, with the double
AFC circuit employed this time, for the jitter the AFCI loop
works best with decreasing the sensitivity and for the phase
distortion the AFCII loop works with increasing the 2VP-P
SYNC
sensitivity. IN
17 20 21
61
(2) The AFC voltage controls frequency (32 x fH) of the
oscillator (VCO).
Fig. 9-5 shows the control characteristics of the VCO.
(3) The H output is obtained by dividing the 32 x fH (503 High
kHz) of the oscillator with flip-flops. Fig. 9-6 shows the
block diagram of this count down circuit.
(4) The V output is created by dividing the 32 x fH
oscillator output into 1/8, and then by counting the 4 x
fH pulse with a vertical counter which is reset with a V
reset pulse (V sync output signal stated under sync Low
separation).
(5) That is, the V output is not created by simply counting
down the H by performing V synchronization with a V
Low High
reset pulse entering within a window provided for V AFC voltage (V)
synchronization --- called direct type sync system, thus,
the circuit can work for non standard signals.
Fig. 9-5
32fH 4fH fH
32 x fH VCO X 1/8 X 1/4 H OUTPUT
V sync Reset
signal V WAVEFORM pulse V
SHAPE V OUTPUT
COUNTER
CIRCUIT
62
SECTION X
VERTICAL OUTPUT CIRCUIT
63
1. OUTLINE
As can be seen from the block diagram, the sync circuit and
the V trigger circuit are contained in Q501 (TA1222N), and
the sawtooth generation circuit and amplifier (V drive circuit)
contained in Q302 (TA8859AP). The output circuit and
pump-up circuit circuits are included in Q301 (TA8427K).
D309
C322 +9V
R309 C308
+27V D301
15 3 C313
R329 6
7
R303
3
4 Q301
Q501 14 Q302 6 L301 R336
C321 2
31 C307
1 5
R320 R307 L462
R301
13 8 R306
Q312 Q311
C314
C306
R313
R330
R344
C305 +27V
C319 R304 R305
Vp S: Switch
Differential
amplifier
L
a
C2
c
R1 C2 R2 V2
V1
R3
Fig. 10-2
64
2. V OUTPUT CIRCUIT
D309
C322 +9V
R309 C308
+27V D301
15 3 C313
R329 6
7
R303
3
4 Q301
Q501 14 Q302 6 L301 R336
C321 2
31 C307
1 5
R320 R307 L462
R301
13 8 R306
Q312 Q311
C314
C306
R313
R330
R344
C305 +27V
C319 R304 R305
Fig. 10- 3
DC=0V
14 15 16
Fig. 10-4
65
2-3. V Output
2-3-1. Circuit Operation yoke. Q3 turns on for first half of the scanning period
The V output circuit consists of a V driver circuit Q302, and allows a positive current to flow into the deflection
Pump-up circuit and output circuit Q301, and external circuit yoke (Q3 1DY C306 R305 GND), and Q4
components. turns on for last half of the scanning period and allows
(1) Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4 a negative current to flow into the deflection yoke
output stage connected in a SEPP amplifies the current (R305 C306 DY Q4). These operations are
and supplies a sawtooth waveform current to a deflection shown in Fig. 10-5.
+27V
D301 C308 50V
D308 V3
27V
Q301
6 3
GND
D309 R309 V7
Q3
7 27V
GND
BIAS V2
CIRCUIT
Q2 2 50V
4 Q4 DY
C306 GND
R305 Q3 ON
GND
1
Q4 ON
Q3
GND (c) Q4 Collector current i2
i1 Vce 1
Q4
GND (d) Deflection yoke current i1+i2
Q2
i2
Vp
Vcc (e)
1/2 Vcc
GND
(a) Basic circuit
Fig. 10-6 Output stage operation waveform
66
(4) To decrease the collector loss of Q3, the power supply (6) Since pin 7 of a transistor switch inside Q301 is connected
voltage is decreased during scanning period as shown to the ground for the scanning period, the power supply
in Fig. 10-7, and VCE1 decreases and the collector loss (pin 3) of the output stage shows a voltage of (VCC-
of Q3 also decreases. VF), and C308 is charged up to a voltage of (VCC-VF-
-VR) for this period.
Q3 Collector loss decreases (7) First half of flyback period
by amount of this area Current flows into L462 D1 C308 D308 VCC
(+27V) GND R305 C306 L462 in this order,
Power supply
for flyback period (Vp) and the voltage across these is:
Power supply VP=VCC+VF+(VCC-VF-VR)+VF about 50V is
for scanning period applied to pin 3. In this case, D301 is cut off.
(Vcc)
(8) Last half of flyback period
Current flows into VCC switch D309 C308
Scanning period
Q301 (pin 3) Q3 L462 C306 R305 in this order,
and a voltage of
VP=VCC-VCE (sat)-VF+(VCC-VF-VR)-VCE (sat),
about 40V is applied to pin 3.
Flyback period
(9) In this way, a power supply voltage of about 27V is
Fig. 10-7 Output stage power supply voltage applied to the output stage for the scanning period and
about 50V for flyback period.
D308
Q301 Q301
6 3 6 3
D309 R309 D309 R309
Switch Switch VR
Q3 7 Q3 7
D1 D1
First half
L462 L462
2 2
Q4 Q4
C306 C306
R305 R305
Last half
Fig. 10-8
67
2-4. V Linearity Characteristic Correction
68
SECTION XI
HORIZONTAL DEFLECTION CIRCUIT
69
1. OUTLINE
Q501
R433
D430 BB81
81 81 22 H Vcc
BB80 L400
70
3. BASIC OPERATION OF HORIZONTAL
DRIVE
turn off the transistor, a sufficiently high, reverse voltage
A sufficient current must flow into base of the horizontal
must be applied to the base.
output transistor to rapidly make it into a saturated (ON)
(3) When the transistor is on (collector current is maximum)
condition or a cut off (OFF) condition. For this purpose, a
condition with the sufficiently high forward voltage
drive amplifier is provided between the oscillator circuit and
applied to the base, the transistor can not be turned off
the output circuit to amplify and to waveshape the pulse
immediately, if a reverse base bias is applied to the base
voltage.
because minority carriers storaged in the base can not
be reduced to zero instantly. That is, a reverse current
3-1. Theory of Operation
flows through an external circuit and gradually reduces
(1) The horizontal drive circuit works as a so called switching
to zero. The time lag required for the base current to
circuit which applies a pulse voltage to the output
disappear is called a storage time and falling time.
transistor base and makes the transistor on when the
(4) To shorten the storage time and the falling time, a
voltage swings in forward direction and off in reverse
sufficiently high reverse bias voltage must be applied to
direction.
allow a heavy reverse current to flow. This operation
(2) To turn on the output transistor completely and to make
also stabilizes operation of the horizontal output
the internal impedance low, a sufficiently high, forward
transistor.
drive voltage must be applied to the base and heavy base
current ib must be flown. On the contrary, to completely
+
Forward
ib current
0 t Base current (c)
Reverse
current
V -
Falling
(a) time
Storage
time
Fig. 11-2
71
3-2. Drive System 3-2-2. OFF drive system
3-2-1. ON drive system When the drive transistor is on, the horizontal output transistor
When the drive transistor is on, the horizontal output transistor is off.
also turns on.
Merit:
Merit: • Energy balance between on and off periods of the drive
• The base current can be precisely controlled without circuit is better, and the circuit can be simplified.
being affected by variation of pulse width which is • Reverse base current of the horizontal output transistor
caused by the horizontal oscillator circuit and the drive can be controlled easily.
circuit.
Demerit:
Demerit: • Base-emitter forward current flowing into the horizontal
• It is difficult to flow a reverse bias current to the horizontal output transistor is susceptible to on-period variation of
output transistor to eliminate its storage carrier for transient the drive transistor.
period of on to off period for the horizontal output
transistor.
H output H output
H driver H driver
H OSC H OSC
ON +B ON ON +B ON
(OFF) (OFF) (OFF) (OFF)
72
3-3. Circuit Description
Q501
H. Vcc
22 T401
H drive
transistor
Q402
H drive
transistor + V1
R416 V2
0V
C416
9V +125V
VCP
0V
Q402 Q402
OFF ON
Fig. 11-5
73
4. HORIZONTAL OUTPUT CIRCUIT
10 HV
5
2 T461
FBT
S-charactor
3 capacitor
Q404 L462
H output 1 8 Deflection yoke
(With damper diode) (H coil)
IC501 T401
H drive C440
transformer
R415
H. out C444
TP-33
Q402 D461 C442 R441
H drive
BB31
C463
Q1 23 33
R411 C417 C423 L442
C467
R410
L441
L461
C413
+
C416 C464 H
R416
Resonat + M-charactor linearity
capacitor correction coil
To DPC output
Fig. 11-6
74
4-1. Theory of Operation
Description of the basic circuit
4-1-1. Operation of Basic Circuit
1. t1~t2:
(1) To perform the horizontal scanning, a 15.734 kHz
A positive pulse is applied to base of the output transistor
sawtooth wave current must be flown into the horizontal
from the drive circuit, and a forward base current is flowing.
deflection coil. Theoretically speaking, this operation
The output transistor is turned on in sufficient saturation
can be made with the circuit shown in Fig. 11-7 a and
area. As a result, the collector voltage is almost equal to the
b.
ground voltage and the deflection current increases from
(2) As the switching operation of the circuit can be replaced
zero to a value in proportionally. (The current reaches
with switching operation of a transistor and a diode, the
maximum at t2, and a right half of picture is scanned up to
basic circuit of the horizontal output can be expressed
this period.)
by the circuit shown in Fig. 11-7 a. That is, the transistor
can be turned on or off by applying a pulse across the
2. t2:
base emitter. A forward switching current flows for on-
The base drive voltage rapidly changes to negative at t2 and
period, and a reverse switching current flows through
the base current becomes zero. The output transistor turns
the diode for off-period. This switching is automatically
off, collector current reduces to zero, and the deflection
carried out. The diode used for this purpose is called a
current stops to increase.
damper diode.
3. t2~t3:
The drive voltage turns off at t2, but the deflection current
can not reduce to zero immediately because of inherent
nature of the coil and continues to flow, gradually decreasing
by charging the resonant capacitor C0. At the same time, the
capacitor voltage or the collector voltage is gradually
increases, and reaches maximum voltage when the deflection
a H output basic circuit current reaches zero at t3. Under this condition, all electro-
magnetic energy in the deflection coil at t2 is transferred to
H output the resonant capacitor in a form of electrostatic energy.
transistor
D Co L
Deflection
4. t3~t4:
Damper Resonant yoke Since the charged energy in the resonant capacitor discharges
diode capacitor through the deflection coil, the deflection current increases
in reverse direction, and voltage at the capacitor gradually
Vcc reduces. That is, the electrostatic energy in the resonant
capacitor is converted into a electromagnetic energy in this
b H output equivalent circuit process.
5. t4:
SW1 SW2 Co L When the discharge is completed, the voltage reduces to
zero, and the deflection current reaches maximum value in
reverse direction. The t2~t4 is the horizontal flyback period,
and the electron beam is returned from right end to the left
end on the screen by the deflection current stated above. The
Vcc operation for this period is equivalent to a half cycle of the
resonant phenomenon with L and C0, and the flyback period
is determined by L and C0.
Fig. 11-7
75
6. t4~t6: t1 t2 t3 t4 t5 t6
For this period. C0 is charged with the deflection current
A TR 0
having opposite polarity to that of the deflection current base voltage
stated in "3.", and when the resonant capacitor voltage
exceeds VCC, the damper diode D conducts. The deflection
current decreases along to an exponential function B TR 0
(approximately linear) curve and reaches zero at t6. Here, base current
operation returns to the state described under "1.", and the
C TR
one period of the horizontal scanning completes. For this collector
current 0
period a left half of the screen is scanned.
In this way, in the horizontal deflection scanning, a current D D 0
flowing through the damper diode scans the left half of the damper
current (SW2)
screen; the current developed by the horizontal output
transistor scans the right half of the screen; and for the E Switch
flyback period, both the damper diode and the output transistor current 0
(TR, SW1)
are cut off and the oscillation current of the circuit is used.
Using the oscillation current improves efficiency of the F Resonant
circuit. That is, about a half of deflection current (one fourth capacitor
current (Co) 0
in terms of power) is sufficient for the horizontal output
transistor.
G Deflection
current (Lo) 0
H TR
collector
voltage 0
Fig. 11-8
76
4-1-2. Linearity Correction (LIN)
(1) S-curve Correction (S Capacitor)
t2 t1 t2 t1
Pictures are expanded at left and right ends of the screen even
if a sawtooth current with good linearity flows in the deflection q2 q1 t2 = t1 q2 q1 t2 > t1
coil when deflection angle of a picture tube increases. This q 2 < q1 q2 = q 1
is because projected image sizes on the screen are different
at screen center area and the circumference area as shown in
Fig. 11-9. To suppress this expansion at the screen
circumference, it is necessary to set the deflection angle @
to a large value (rapidly deflecting the electron beam) at the
screen center area, and to set the deflection angle @ to a small
value (scanning the electron beam slowly) at the (a) S-character correction (b)
circumference area as shown in Fig. 11-9.
In the horizontal output circuit shown in Fig. 11-10, capacitor
CS connected in series with the deflection coil LH is to block
Fig. 11-9
DC current. By properly selecting the value of CS and by
generating a parabolic voltage developed by integrating the
deflection coild current across the S capacitor, and by varying Cs
the deflection yoke voltage with the voltage, the scanning
speed is decreased at beginning and end of the scanning, and
TR
increased at center area of the screen. The S curve correction D Co
LH
is carried out in this way, thereby obtaining pictures with
good linearity.
Deflection coil
Vcc
Slow deflection
Fig. 11-10
77
total are obtained.
(a)
FBT
TR LH LH
D Co Deflection
coil TR
D Co
LI
iH Li Vcc L
Cs Cs
S-character C
capacitor
(b) Deflection coil current
(iH)
Resistance of LH
(b) Sawtooth wave current
0 Characteristic of D
(Left) (Right)
(Left) (Right)
Current (A)
Fig. 11-12
Fig. 11-11 Linearity coil
78
which has two times the H oscillator frequency.
AFC CRT
10
blanking anode
Heater 9
C303
4
Auxiliary +27V
winding
D302 7
C310
R327
6
C460 Focus
D460 R469
-27.5V 5
D406
+210V 3
C446
Primary +125V 2
winding
C448
1
D404 ABL
Screen
T401
L441 R441
1000VP-P
0
C442
1H
(15.75KHz)
Fig. 11-13
79
5-1. Theory of Operation
5-1-1. +210V
For the flyback period, pulses are stacked up to DC +125V
with FBT, and the voltage is rectified by D406 and filtered +115V
by C446.
5-1-2. +27V 0
Pin 4 of the FBT is grounded and the shaded area of negative
pulse developed for opposite period of the flyback period is
Fig. 11-14
rectified, thus developing better regulation power supply.
5-1-3. -27V
As a power for the DPC circuit, a negative pulse signal is 10 0
rectified by D460 and filtered with C460, thus developing
4
the -27V.
7 0
5-1-4. High voltage
Singular rectification system which uses a harmonics non- For +27V
8
resonant type FBT is employed and a better high voltage
regulation is obtained, so amplitude variation of pictures 2
0
becomes low.
1
Fig. 11-15
F G
Pulse
E
Picture
tube anode E
F
Primary Picture
tube capacitor
D EH
D Stacked
C C pulse of
4 block
EO
B B
Auxiliary A
A
1H
ABL 15.735KHz
Fig. 11-16
80
5-2. Operation Theory of the Harmonic Non-Resonant System and Tuned Waveforms
Flyback
pulse 11ms
Reference 1 1
= = 45KHz
wave 22ms 22x10
20ms
45 KHz
AC
0 Tuned
waveform
(In case of 3X) (In case of 15X)
Hight
voltage E E
81
frequency, and the turned waveform is shown in Fig. 11-17.
1. Outline
In case picture tube using high voltage, when high voltage
rises abnormally due to components failure and circuit
malfunction, there is possible danger that X-RAY leakage
increases to affect human body. To prevent it, X-RAY
protection circuit is equipped.
2. Operation
Figure 10-18 shows the circuit diagram. Supposing high
voltage rises abnormally due to some reason, pulse at pin 9
of T461 also rises, and detection voltage Eb rectified by
D471 and C471 in X-RAY protection circuit rises. When Eb
rises, emitter voltage of Tr10 divided by R25 and R26 in
protector module becomes higher than [zener voltage (6.2V)
of ZD6 + Tr10 VBE ]. This causes Tr10 turns on to supply
base current to Tr9. Then Tr9 turns on. By this Tr6 and Tr6
turn on to make ON/OFF pulse at pin 7of QA01 in low level,
QB30 and Q843 turns off, then relay SR81 turns off. Tr6 and
Tr7 are in thyristor-connection, and 5V of power holds
protection operation until main power switch is turned off.
During circuit operation, power LED near main power
switch blinks in red. Caution : To restart TV set, repair failure
5V
15
12V
MICOM
R9
QA01#7
R10
R25 R472 T461
Tr10 ED
Tr7 Tr9 13 9
RB30 D471
R21 R26
RELAY R20
Tr6
SR81 R22 C471
D3
R12 ZD6
16 Tr5 C1
Q843 QB30
R11
12
+ C474
82
first.
1. Outline
If main power (125V) current increases abnormally due to
components failure, there is possible danger of the secondary
damage like failure getting involved in other part failure, and
abnormal heating. To prevent this, over current protection
circuit is equipped, which detects current of main B line to
turn off power relay in abnormal situation.
2. Operation
Fig. 11-19 shows over current protection circuit. When the
current of main B line increases abnormally due to the
shortage in load of main B line, voltage drop arises across
R470. By this voltage drop, when base-emitter voltage of Tr
8 in protector module (Z801) becomes appprox. 0.7V or
more, Tr 8 turns on, and the voltage by divided ratio of R15
and R16 is applied to cathode of ZD4. When this voltage
becomes higher than zener voltage of ZD4, ZD4 turns on to
supply base current to base of Tr 6 via R14. This causes Tr
5 ON and voltage at pin 16 of Z801 becomes Low. Therefore,
QB30 and Q843 turns off to set SR81 OFF. Tr 6 and Tr 7 in
Z801 are in thyristor- connection, and power 5V-1 supplied
at pin 15 keeps protection operation for standby power until
main power switch is turned off. During circuit operation,
power LED near main power switch blinks in red. Caution :
R470 F470
MAIN B To T461
R479 R472
5V
C472
15 2 1
MICON
R9
QA01#7
ZD4
R830 R16
R10
Tr7
RELAY Tr8
SR81
R14 R15
16 Tr6
Q843 Q830
R12 C1
Tr5
Z801
R11 PROTECTOR MODULE
Z801
PROTECTION MODULE
17
Q404
C444 C440 L642 D442 R442
C442 C441
+
Cs lp ls L461
- D461 SIDE DPC C448
C467 C464
FBT
Fig. 11-20
Fig. 11-23
T461
L462
D442
l1
Vcs
R442
C442
C441 C448
Vcs MAIN
Fig. 11-21 iB B
Fig. 11-24
Kink in the cross bar
pattern
Fig. 11-22
84
SECTION XII
DEFLECTION DISTORTION
CORRECTION CIRCUIT
(Side DPC Circuit)
85
1. DEFLECTION DISTORTION
CORRECTION IC (TA8859P)
(3) V S-character correction
1-1. Outline
(4) V picture position (neutral voltage setting)
The deflection distortion correction IC (TA8859AP), in
(5) V M-character correction
combination with a V/C/D IC (TA8859AP) which has a V
(6) V EHT correction
pulse output, performs correction for various deflection
(7) H amplitude
distortions and V output through the I2C bus control. All the
(8) L and R pin-cushion distortion correction I (entire area)
I2C bus controls are carried out by a microcomputer and can
(9) L and R pin-cushion distortion correction II (corner
be controlled with the remote control.
portions at top and bottom)
(10) H trapezoid distortion correction
1-2. Functions and Features
(11) H EHT correction
The IC has functions of V RAMP voltage generation, V
(12) V AGC time constant switching
amplitude automatic switching (50/60 Hz), V linearity
correction, V amplification, EHT correction, side pincushion
1-3. Block Diagram
correction, I2C bus interface, etc. and controls following
Fig. 12-1 shows a block diagram of the basic circuit.
items through the I2C bus lines.
(1) V amplitude
(2) V linearity
+12V
14 15 16 5 3
Control Through
H. Trapezoid Distortion Bus
Correction
V. M-Character V. Linearity V. S-Character
Correction Correction Correction
L-R Pincushion
Distortion Correction I
(Bus Control Signal)
SDA SCL
L-R Pincushion
Distortion Correction II
V. Amplitude
10 (Top & Bottom Comer Section)
Adj.
9 Logic
V. Screen V. EHT H.EHT H.EHT
12 Position Correction Input Corrction
H. Amplitude 2 EW-Drive
Adj.
8 6 1 4
V Drive V. Feedback EHT INPUT EW Feedback
Fig. 12-1
86
2. SIDE DPC
V. Sync
H. Sync
Fig. 12-2
87
3. DIODE MODULATOR CIRCUIT
high voltage of FBT also develops a constant voltage.
Fig. 12-4 shows a basic circuit of the diode modulator used
When the negative pulse developed at the point B is integrated
in the N5SS.
with Lm and Csm, its average value appears at Csm as a
A key point in the N5SS chassis shown in Fig. 12-4 is to
negative voltage.
develop a negative pulse at point B.
By modulating this voltage to have the parabolic curve with
In this circuit, a current loop of the resonant circuit for
Q460, a waveform of Vm is obtained as shown in Fig. 12-6.
flyback period is shown by an arrow, and the energy stored
As a result, the voltage Vs which is the sum of the power
in LDY is transferred to resonant capacitors Cr, Crm in
supply voltage VB and the Vm is applied across the S-curve
passing through Cr, Crm, Cs when the scanning completes.
capacitor Cs. The Vs becomes as a power source for the
As a result, a positive, horizontal pulse as shown in Fig. 12-
deflection yoke, and the waveform modulated in the parabolic
5 (a) will appear at Cr, and the current flows into Crm with
form, as shown in Fig. 12-2 (b), is applied to the horizontal
the direction as shown. Then a pulse as shown in Fig. 12-5 (b)
deflection yoke and corrects the left-right pin-cushion
develops at the point B.
distortion.
On the other hand, since constant amplitude pulses across Cr,
as shown in Fig. 12-5, are applied to the primary winding, the
A
FBT
LDY
DD Cr
H
OUT VB
Cs Vs
a) Waveform at point A
B Lm
DM Q460 Vm
Crm Csm
b) Waveform at point B
VB
VS
0
Vm
Fig. 12-6
88
4. ACTUAL CIRCUIT
In the actual circuit, the resonant capacitor is split into two as IP1 IP2 FBT
89
4-1. Basic Operation and Current Path 4-1-2. First Half Scanning Period
4-1-1. Later Half Scanning Period When the base drive current decreases and the H. OUT
When the power is turned on, the power supply voltage VB transistor is turned off, each energy stored in LDY, Lm, Lp
is applied to Cs and Csm, and the Cs acts as a power source of FTB is transferred to C1, C2 and C3, respectively, and the
for a later half of the scanning period for which the H. OUT resonant current becomes zero at a center of the flyback
transistor is turned on, and the deflection current Iy flows in period. Then, VA and VB pulses show a maximum amplitude.
the path as shown below
VA
VA
FBT FBT
LDY LDY lP
IY lP IP1 IY
H.OUT C1 C2
+ IY2
Cs IP2 Cs
VB
VB VB VB
IM LM IM LM
IDC
DM IDC
CSM
+ CSM
IY 0
VA 0
IM 0
VA IDC
0
IM 0
IDC VB 0
VB 0 C1: IY1+IP1
C1
C2: IY2+IP2
C2 0
Fig. 12-10
C3: I P2-IY1-IM
C3 0
Fig. 12-12
90
4-1-3. Later Half of Flyback Period 4-1-4. First Half of Scanning Period
All energy in the coil has been transferred to the resonant When the flyback period completes, the damper diode DD
capacitors at the center of the flyback period, and the voltage and the modulation diode DM turn on, and the Iy and Im
shows the maximum value. However, during next half of the proportionally decrease from the maximum value to zero.
flyback period, the energy of the resonat capacitor is The H. OUT transistor is turned on just preceding at the
discharged as a reverse current through respective coil. center of the scanning period, and repeats the steps 4-1-1
When the discharge has been completed, VA and VB becomes through 4-1-4 stated above.
zero, and the deflection current in reverse direction becomes
the maximum.
VA VA
L.O.P.T
FBT
LDY LDY
IP2 IY
IP1 IP
C1 C2 DD IY
CS CS
IY2
IY1
VB VB VB
C3 VB
IM LM IM LM
DM
IDC IM
CSM CSM
Iy 0
IY 0
VA 0
VA
0
IM 0
IDC IM 0
IDC
VB 0
VB 0
C1: I Y1+IP1
C1
C2: I Y2+IP2
C2 0
Fig. 12-16
C3: I P2-Iy1-IM.
C3 0
Fig. 12-14
91
SECTION XIII
CLOSED CAPTION/EDS CIRCUIT
92
1. OUTLINE
P P
b1 b3 b5 b7
A b1 b3 b5 A b7
10.076ms b2 b4 b6 R b2 b4 b6 R
I I
T T 20ms
Y Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
93
3. DISPLAY FORMAT
SCREEN
LINE 43
ROW1
(Yellow)
94
4. CIRCUIT OPERATION
95
UM01 EDS/CC/RGB SW.
Video
in HD
V-AV EH 9 ATT LPF 7 VIDEO HIN 5 INVERTER 11 30 HD OUT
VD
VIN 13 12 31 VP OUT
Q89- I2 C BUFFER
BOX 17 2 1A
96
SCK
SCL1 37 2 SCL1 SCL2 6 13 15 SCK R 18 5 2A
SDA
SDA1 38 3 SDA1 SDA2 5 14 14 SDA G 2 3 3A
Ys OUT
B 3 14 4A 1Y 4 6 36 OSD YS
R OUT
2Y 7 1 37 OSD R
G OUT
1 A/B 3Y 0 5 38 OSD G
B OUT
4Y 12 2 39 OSD B
OSD-YS 18 3 1B
OSD-R
R 22 19 6 2B
OSD-G
G 23 20 10 3B
B 24 OSD-B
21 13 4B
12
VDD
8 Display
Sllce Level SYNC Sllcer RAM
Fig. 13-5 QM01 block diagram
CSYNC
13
VIN
Horizontal R
Counter Output 18
G
Logic 2
DOT CLK B
3
Box
SMS
SDO
SEN
SCK
SDA
17
Phase/
Loop VCO
Freq
Filter
DET
PFD Loop 6 4 15 14 16
FIL Vss AVSS
HIN 5 9 1 11
LPF
SECTION XIV
POWER CIRCUIT
98
1. OUTLINE
T461
+200V
+27V
+27V
R370 4132
AD BE
Q370
T840 OVER VOLTAGE
F801 T801 +12V PROTECTOR
POWER
TRANS Q840 +5V-1 MICOM
TPW PERIPHERALS (Q462) -27V
1459AZ D840
99
2. RECTIFYING CIRCUIT AND STANDBY
POWER SUPPLY
diode and performs rectification and smoothing together
Rectifying circuit is a circuit to generate dc from ac 120V.
with C810. R801 is a resistor to regulate inrush current
D899 is a varistor to absorb surge (ex. lightning) arose
and to suppress rush current in switch-on. T840 is standby
on ac line. When surge arises, the circuit let surge by-pass via
power transformer. D840 and C840 performs rectifying
route shown in figure 13-2 to protect the following
and smoothing to make approx. 12V for relay driving, and
circuit. C801 and T801 are a filter circuit to suppress
Q840 regulator makes +5V to supply to microcomputer
abnormal radiation. Degaussing circuit using thermistor is
and also to output the reset signal of microcomputer.
equipped at after SR81 relay. R811 is a damping resistor to
remove light regulator noise. D801 is a bridge rectifier
L901
R811
Rectified
F801 D899 C801 output
D801
THERMISTOR C810
R810
Surge T801
+3V-1
QB30 MICOM
Q863
POWER
SR81
Q840
1 5 +5V (to MICOM)
C840
2 4 Reset
3
C842
T840 D340
C843
100
4. OUTLINE OF CURRENT RESONANT
TYPE SUPPLY
Basic configuration of current resonant type power supply
used in CN32E90 is shown on figure 14-3. Basic operation
is as follow. Primary winding of converter trans and resonant
capacitor are connected in series to consist of LC series
resonant circuit. And this is drived by push-pull of two power
MOS FET’s. Converter transformer operates in forward
mode. Just when primary switching device turns ON,
converter trans produces the secondary output.
Automatic voltage control operation is done in such way that
+B voltage is detected by error amp. to be fed back to
the primary OSC circuit via photo coupler, then controls
frequency.
D
O R
S I +B
C V
E
ERROR
AMP
PHOTO
COUPLER
5. FUNDAMENTAL THEORY
VL
e
Frequency
Resonant point
1
f=
2p LC
101
6. ACTUAL CIRCUIT
Two MOS FET’s, driver which drives FET’s and frequency control IC are combined inside HIC (Q801 ).
Converter transformer T862 is designed to have loose coupling between the primary and the secondary, and to have
some extent of leakage inductance. This is the reason why L and C (leakage inductance and resonant capacitor) are
resonated during period that rectifying circuit (diode) connected to the secondary winding conducts. Rectifying
circuit of the secondary winding uses double wave rectifier considering current balance of switching device, because
converter transformer is driven in push-pull. The function of STR-Z3201 is explained below. Fig. 14-6 shows
block diagram and figure 14-7 shows waveforms at main terminals.
<<FUNCTION OF HIC>>
(1) Output switching element
Uses two power MOS FET’s, and operates in push-pull. Voltage across the switching element does not increase more than
power line voltage basically, and therefore, element of low rating voltage (enduring 200V) is used.
(2) Driving circuit
Drives output switching element. MOS FET is specially used for driving element of high side, and to drive this, bootstrap
circuit is equipped.
(3) Dead time
To avoid that two switching element turns ON at the same time in push-pull operation, dead time is arranged.
(4) CT terminal (Pin 5) About basic oscillation
Variable frequency oscillator is equipped inside frequency control IC, charge and discharge of the capacitor C862
connected to this terminal decide oscillation frequency and dead time. This oscillator generates triangle wave signal with
low level of 2.5V(TYP) and with high level of 4V(TYP). Charging time of oscillator becomes output-on period, and
discharging time becomes dead time.
(5) RT terminal (Pin 5) About lowest oscillation frequency
Lowest oscillation frequency is decided by capacitor C862 connected to pin 4 and resistor R867 connected to this terminal.
(6) CONT terminal (Pin 6) About frequency control
Current flowing out of this terminal varies charging current of oscillating capacitor C862. Therefore, flowing of CONT
terminal current corresponding to feedback quantity from photo coupler (Q862) varies charging time of C862 and controls
oscillation frequency. Maximum oscillation frequency is decided by R864 connected to CONT terminal.
(7) Css terminal (Pin 8) About soft start
Capacitor (C866) and resistor (R863) for soft start are connected to make TV start at high frequency in the time of power
on and gradually make frequency lower. This function suppresses rush current in POWER MOS FET output and provides
stable starting of TV.
(8) CD terminal (Pin 9)
Latch circuit detects abnormal operation to hold the status of operation seizing, and if following condition as a result of
detecting abnormal operation comes, the latch circuit begins to start.
*In operation of over voltage protection (OVP) circuit
*In operation of thermal shock detection (TSD) circuit
*In operation of over current protection (OCP) circuit
*In going down and no recovery of Main +B output voltage
Until latch function begins to operate, the charging time of capacitor C869 connected to CD terminal (Pin 9) is utilized
to produce delay time. To release the latch function after operating once, turn off power and turn on again.
(9) OC terminal (Pin 12) About over current protection (OCP) function
This is to detect current in LC series resonant circuit, and to suppress over current to stop operation.
(10) Over voltage protection (OVP) circuit
This is to make latch circuit operate when voltage at Vcc terminal (Pin 10) exceeds 22V (TYP).
(11) Thermal shock detection (TSD) circuit
This is to make latch circuit operate when temperature inside IC exceeds 150°C.
102
<< BLOCK DIAGRAM AND PIN FUNCTION >>
Vcc VB HO G(H)
10 16 3 2
R1
CD 9 DELAY LATCH REF Logic
15 OUT
OSC R2
OC 12 OC CONTROL OSC
14 COM
R4 R3
8 6 5 7 4 11 13
103
DATE TIME
=4V
CT PIN VOLTAGE
=2.5V
(PIN11) ON OFF
LOW SIDE
GATE VOLTAGE
(PIN2)
HIGH SIDE OFF ON
GATE VOLTAGE
OV
(PIN 15)
PUSH-PULL
OUT CURRENT
OA
104
7. OTHER POWER CIRCUIT
-27V
AFC FBT
BLANKING 10 ANODE
HEATER 9
R642
5
C461 D460 4
FOCUS
C3\7
7
R327
+27V 6
C310 D302
D406
200V 3
SCREEN
+B 2
C448
Q404 1 8 ABL
Collector
105
8. PROTECTOR MODULE (Z801)
line, Tr8 turns on to supply base current into Tr6 through
CN32E90 employs protector module which combines in one
ZD4. In case of X-RAY protection circuit, when high voltage
package protection circuits for X-RAY protection and over
increases abnormally, Tr10 and Tr9 turns on to supply base
current protection, and error amplifier for +B voltage
current into Tr6 through D3, then this causes Tr6 and Tr5
detection. This is for the purpose of small size and
turn on to make power signal from microcomputer in low
standardization of protection circuit, and what were discrete
level. Besides, by the positive feedback that turning on of
circuits in conventional chassis are arranged into module.
Tr6 causes Tr7 turn on to make base current flow to Tr6, as
Equivalent circuit is shown in figure 14-9. A section is error
long as 5V is supplied to pin15, Tr5, Tr6 and Tr7 continues
amplifier for +B voltage detection, B section is over current
to be on to keep safety. Therefore the operation is not
protection circuit and C section is X-RAY protection circuit.
released by remote control, but continues until AC cord is
D section forces power signal from microcomputer to set in
pulled and inserted. When this module operates, red blinking
low level by the signal from protection circuits, and to turn
of power LED shows the operation of protection circuit.
OFF the power relay and keep it. Actually in case of over
current protection circuit, when over current flows in +B
R470
+25V over voltage
+B
POWER protection
Q862 +27V over current
X-RAY
protection
R472 R479
C470
R890
C474 +25V
5V-1
5 3 16 15 6 2 1 14 12 13 11
R25 R23
Tr9 Tr10
A R9 R19
R16 D1 R20
R2
ZD4
R10 Tr8
Tr7 D3
B
D R14 R15
Tr1 R21 R22
C
Tr6
R12
R3 C1 R26
Tr5 R11
ZD1
7 17
Pins 4, 8, 9,10: No connection
106
TROUBLESHOOTING CHART OF POWER CIRCUIT
No raster
17 23
9
YES
Fuse F801 breaks Check/Repair AC circuit Replace F801
No 18 24
10 Is the following
YES YES
point short? Replace
Fuse F860 breaks #1-#14, #1-#15, Q801, F860
#14-#15 of Q801
No
No 25
Replace F860
26
19
Instantly turns ON and 11
then turns OFF immediately OK NG Check/Repair
Check relay SR81 Voltage across C810 D801, R810
C810
1 20
12 27 31
NG
NG NG
Check/Repair Check voltage across Does pin 15 of Q801
Voltage across C868 Check/Repair
T840, D840 C840 operate in switching?
C868, D864,
28 R871, D876,
2 OK R861
13
No Check/Replace
Check/Repair OK Instantly switching Q801, C870, T862
Voltage at pins 4 and then stops
T840 or 5V-1
and 5 5V? immediately
using circuit 30
OK
34
YES 16
5 NG
Is voltage at pin 22 (H-Vcc)
Voltage across C884 Check/Repair Q801, D883, of Q501 9V?
jumps instantly to D884, Z801, R883, R884,
140V or more Q862, R864
35 OK
No
6 Check peripherals of start
circuit Q430 and audio Vcc
Z801 makes over current protection circuit,
X-RAY protection circuit and +27V over
voltage protection circuit operate
36 37
NG
7 Check R920 and
Check deflection Does heater light?
circuit CRT Drive board
OK
38
Check peripherals of
Q501 and video out circuit
107
(No RASTER)
8
No RASTER
1
4 10
NG Red lights
Check/Replace Is the status of power
Check F470
F470, Q404 LED?
OK Red blinks
5
Is voltage at pin 22 (H-Vcc)
NG of Q501 9V?
2 OK
21
Check peripherals of 13
LED
start circuit Q430
Short R370 and turn Red blinks Check peripherals of V.out
and audio Vcc
power on again circuit Q301 and +27V line
(See note below.)
3 6 22
15
NG LED
Check R920 Check H. out circuit;
Does heater light? Open R472 and turn Red blinks
CRT Drive board C440, C444 and X-RAY
power on again
(See note below.) protection circuit
OK (including Z801)
7
Red blinks
Check peripherals of 17 23
Q501 and video out
circuit Short R470 and turn F470 blinks
power on again Check main B line and
H. out circuit (Q404, 4T461)
(See note below.)
Red blinks
19
108
SECTION XV
DSP CIRCUIT
109
1. ORIGINS OF DOLBY SURROUND into left, center equally into left and right, and right into
right-playing a Dolby Stereo soundtrack over two speakers
Dolby Stereo movies and Dolby Surround video and television reproduces the entire encoded soundtrack. There is but one
programs include an additional sonic dimension over exception: the surround signal, though audible, is not
conventional stereo productions. They are made using a Dolby reproduced in its proper spatial perspective. When the first
MP (Motion Picture) Matrix encoder, which combines four home decoder was developed in 1982, its goal was to restore
channels of audio into a standard two-channel format, suitable this lone missing dimension.
for recording or transmitting the same as regular stereo programs. Before we discuss decoders, it is necessary to see how the MP
To recapture the dimensional properties brought by the Matrix encoder works. Referring to the conceptual diagram
additional channels, a Dolby Surround decoder is used. In in Fig. 15-1, the encoder accepts four separate input signals;
the theatre, a professional decoder is part of the Dolby Stereo left, center, right, and surround (L, C, R, S), and creates two
cinema processor used to play 35 mm stereo optical prints. final outputs, left-total and right-total (Lt and Rt).
The decoder recovers the left, center, and right signals for
playback over three front speakers, and extracts the surround The L and R inputs go straight to the Lt and Rt outputs without
signal for distribution over an array of speakers wrapped modification, and the C input is divided equally to Lt and Rt
around the sides and back of the theater. (These same with a 3 dB level reduction (to maintain constant acoustic
speakers may also be driven from four of the six discrete power). The S input is also divided equally between Lt and Rt,
tracks on 70 mm Dolby Stereo magnetic prints, but in this but it first undergoes three additional processing steps:
case no decoder is needed.) a. Frequency bandlimiting from 100 Hz to 7 kHz.
Home viewing of movies on video has become extremely b. Encoding with a modified from of Dolby B-type noise
popular, and with the advent of stereo VCR's, stereo television reduction.
and digital video discs, the audio side of the video presentation c. Plus and minus 90-degree phase shifting is applied to
has improved considerably, inviting the use of full-range create a 180-degree phase differential between the
sound reproduction. The ability to deliver high quality audio components feeding Lt and Rt.
in these formats made it easy to bring MP Matrix-encoded It is clear there is no loss of separation between the left and right
soundtracks into the home as well, thus establishing the signals; they remain completely independent. Not so obvious
foundation for Dolby Surround. is that there is also no theoretical loss of separation between the
center and surround signals. Since the surround signal is
2. THE DOLBY MP MATRIX recovered by taking the difference between Lt and Rt, the
identical center channel components in Lt and Rt will exactly
One of the original goals of the MP Matrix was to enable cancel each other in the surround output. Likewise, since the
Dolby Stereo soundtracks to be successfully played in theaters center channel is derived from the sum of Lt and Rt, the equal
equiped for mono or two-channel stereo sound. This allows and opposite surround channel components will cancel each
movies to be distributed in a single optical format, and other in the center output.
furtheremore results in complete compativility with home The ability for this cancellation technique to maintain high
video media without requiring separate soundtrack mixes. separation between center and surround signals requires the
Since the three front channels of the MP Matrix are assembled amplitude and phase characteristics of the two transmission
in virtually the same way as a conventional stereo mix --- left channels to be as close as possible. For instance, if the center
Left + + Lt
+ +
+ +
Right + + Rt
110
channel components in Lt are not identical to the ones in Rt 4. DSP CIRCUIT
as a result of a channel balance error, center information will
come out of the surround channel in the form of unwanted A surround component (L-R) is extracted from L, R audio
crosstalk. signals coming through the AV SW in the matrix circuit as
shown in Fig. 15-3. The surround component enters the DSP
3. THE DOLBY SURROUND DECODER circuit through the LPF.
The signal is A/D converted, delayed by an arbitrary time of
This leads us to the original Dolby Surround decoder. The 0~100 msec (every 3.2 msec) by digital process and then D/
block diagram in Fig.1 5-2 shows how the decoder works. A converted and outputs from the DSP IC. The DSP IC
Except for level and channel balance corrections, the Lt develops two outputs; (LO) for FRONT (LO) and (RO) for
input signal passes unmodified and becomes the left output. REAR and each output is controlled by the microcomputer
The Rt input signal likewise becomes the right output. Lt and for each surround mode. The output signal (LO) for FRONT
Rt also carry the center signal, so it will be heard as a is added and subtracted with the input signal in a matrix
"phantom" image between the left and right speakers, and circuit and output from the front speaker in passing through
sounds mixed anywhere across the stereo soundstage will be the audio processor and main amplifiers.
presented in their proper perspective. The center speaker is At the same time, the output signal (RO) for REAR is fe?? to
thus shown as optional since it is not needed to reproduce the the Dolby NR circuit, but switched to "Dolby surround"
center signal. mode, and then output from the rear speaker in passing
through audio processors and rear main amplifiers.
The L-R stage in the decoder will detect the surround signal In this case, the DSP stands for not only a simple digital
by taking the difference of Lt and Rt, then passing it through surround processor but also a digital surround field processor.
a 7 kHz low-pass filter, a delay line, and complementary That is, it works to give a simple surround effect but to give
Dolby noise reduction. The surround signal will also be effect as if the listener can feel reality suitable for the
reproduced by the left and right speakers, but it will be heard programs. For example, it aims to give the listeners a reality
out-of-phase which will diffuse the image. matching to each program they are enjoying in their home
Since the heart of the decoding process is a simple L-R listening room so that they can obtain reality of big concert
difference amplifier, it is referred to generically as a "passive" hall or feel as if they are watching a move at a reserved seat
decoder. This is to distinguish it from decoders using active in a movie theater.
processes to enhance separation which are known as "active"
decoders.
INPUTS OUTPUTS
L L
Left
Lt R R MASTER
INPUT Right
LEVEL C LEVEL
BALANCE CONTROL Center
CONTROL CONTROL
C
Surround
Rt L+R
Optical passive center siganal S
S ANTI- MODIFIED
L+R ALIAS B-TYPE NR
FILTER DECODER
7 kHz
AUDIO LOW PASS
DELAY SET
DELAY FILTER
111
QD02
From QD08 QD01 DSP Q670
A/V SW Input Balance Input Buffer Front Addition Circuit Front amp
12 14 L 5 7 L L+S
L L
IN 10 8 8 Speaker
R R
R R
R L 10 R-S
9
6 5
7 3 1 3 1 L+R
MATRIX Sycrone
LPF LPF (Super woofer)
(L-R CIRCUIT) (L-R)
QD01 QD01 QD02
VC
TO
112
(H002)
Buffer
VL 7
CONT LO 3 1 5
D/A LPF LO
BUS 7
QD04
From Micro
computer VR Buffer DQ06
RO 3 7 3
D/A LPF
8
QD06 1 Q640
Dolby NR
Rear Amp
6
9 14 L-R +S
L
12
Speaker
QD07 DQ02 R
As shown in Fig.1 5-4, a sound emitted in a sound field can difference between the direct sound and the reflected sound.
be classified as a direct sound which directly reaches ears of For more detail, this situation can be expressed with the
a listener, and reflected sound which comes after collision direct sound, initial reflection sound coming after one time
with a wall as shown by dotted line or comes after several of reflection, and trains of reverberation sound in later period
times of collision as shown by double dotted lines. The as shown in Fig. 15-5.
listeners are determining that they are listing in what type of The DSP circuit develops these initial reflection sound and
location by perceiving time difference and volume level the reverberation sound artificially and add them to the
original sounds, thereby creating rhe effect that allows the
listeners in the home listening room to feel as if they are
listening in an original location.
The DSP IC YM7128B has eight separate output taps and
their delay time and the output levels can be specified
separately, so, various sound fields can be selected by
varying the initial reflection sound. Moreover, the IC has an
internal feedback loop which controls the delay time and the
output level in considering the later time reverberation
sound.
Direct Sound
Initial Reflection
Sound
Reverberation
Sound
Time
113
processing is performed by VC, then it feed-backed to the
5. DSP (Digital Surround Processor) IC delay input after it is added to the doubler described above.
The output of eight taps T1 to T8 is added after performing
Input signal entered into analog input pin 4 of DSP IC QD03 reduction processing by GL1~GL8, GR1~GR8, and reduction
(YM7128B) is converted to 14 bit digital signal with the processing is performed by the digital attenuator VL or VR,
sampling frequency 23.6 kHz by A/D converter of 14 bit and an analog output is created by D/A converter after
floating system, and enters digital delay circuit through passing through digital filter, comes out from pin 7 or 8.
digital attenuator VM and doubler. The digital attenuated value, delay time and the coefficient
The digital delay circuit has nine output taps, and the delay of FIR type low pass filter are set by writing the data on the
time of each tap can be controlled independently, also each register.
tap position can be switched by T0 to T8 register. This process is performed by loading three data from sub
In a minute, the T0 output passes through the primary FIR microcomputer to microcomputer interface.
(Finite Impulse Response) type low pass filter, and reduction This unit has four modes as surround mode. The setting
values are described in Table 15-1.
114
XD01
CD23
115
GL4 VL LO
D/A 7 To LPF Output
/TI GL5 2fs CONVERTER
6 GL6 (For FRONT ch)
DC26
GL7
GL8
GL1
GL2
GL3
GL4 VR RO
D/A To LPF Output
GL5 2fs 8
MICROCOMPUTER CONVERTER (For REAR ch)
INTERFACE GL6 DC25
GL7
The surround circuit used in this model has the modes shown Fig. 15-8 shows the input balance circuit.
in Table 15-2 of the modes, description will be given for 5 The input balance circuit is to adjust gain of Lch and Rch so
mode. The description will be made according to items that (L-R) component in the matrix circuit becomes zero.
shown below. Adjustment by the input balance volume control on the
remote hand unit.
Fig. 15-7
+9V
A/V SW QD08
L OUT + 1
2 L
CD04 Leh
3
1m50V 4 Input buffer
CD09
RD23 5 22m16V
6
15K
7
8
CD05 9
RD24 10
56K 22m 11
4V 12
Reh
R OUT R 13
Input buffer
14
CD06
1m50V
Fig. 15-8
116
8. MATRIX CIRCUIT 9. FILTER CIRCUIT (ANTI-ALIAS
Fig.15-9 shows the matrix circuit. FILTER)
The matrix circuit is to create a surround signal of (L-R) from Fig. 15-10 shows the filter circuit.
the Lch and Rch signals. According, if a monaural signal The filter circuit is to cut frequencies higher than 7 kHz in
enters, L-R=0, showing no surround effect exists. considering processing capacity of the DSP circuit (delay)
connected to next stage, and two stages of the filters are
employed in this unit.
QD01
CD02
Buffer
1m50V (NP)
12
Lch IN 14
13 Lch OUT
RD13
CD02 39K
39K CD15
QD01
39K
5
REF 7
Surround OUT
6 (L-R)
CD03
39K
CD16
RD14 33K
CD03 9 39K
1m50V (NP) 8
10 Rch OUT
Rch IN
QD01
Buffer
Fig. 15-9
Fig. 15-10
117
10. DSP CIRCUIT (DELAY)
Fig.1 5-11 shows the DSP circuit.
The DSP circuit delays the surround signal entered by a time
of digital delay determined for each mode and then outputs
the signal. The DSP circuit is controlled with 3 line-bus data
from the sub-microcomputer. The DSP circuit develops two
type of outputs; one for front addition and the other for rear
output. Details of the outputs are shown in Table 15-2.
Bus data
16 15 14 13 12 11 10 9
DIN AD SCI XI XO
DSP
QD
YM7128B
Ycc CH IN CY Lo Ro
1 2 3 4 5 6 7 8
LPF
Rear OUT
Surround IN
LPF
(L-R)
Front OUT
Fig. 15-11
118
11. 7 kHz LOW PASS FILTER
The DSP outputs are received at inputs of high impedance
voltage followers and then fed to 7 kHz LPFs. Since L and
R components of the DSP output are processed in time
sharing by the D/A converter, the LO and RO outputs must
be received at the high impedance input circuits. The LPFs
which receives the signals consist of OP amplifiers.
CD39
M5600P
QD03
CD32
1m50V QD05 RD30 RD29 RD28 QD05
DSP 3 10K 10K 10K
LO 7 1 5
2 7 Front
6
CD26 (Addition circuit)
RD31 CD31 CD30
33P 1M 820P
M3300P
REF
CD17
RD34 M6800P
1M
QD06 RD47 RD46 RD45
5 QD06
DSP 7 10K 10K 10K
8 3
RO 6 1
CD34 2 Rear
1m50V (Dolby NR circuit)
CD25 CD19 CD18
33P M2700P 390P
Fig. 15-12
119
12. DOLBY NR CIRCUIT
Fig. 15-13 shows the Dolby NR circuit.
The Dolby NR circuit used in this unit is a modified B type
for Dolby surround and the operation characteristics are
shown in Fig. 15-14. RD61
47K
RD60
47K
RD66 RD65
18K 150
16 15 14 13 12 11 10 9
Dolby QD02
12
N.R 14
QD07 Rear OUT
TA7629P REF
13 CD46
4.7m16V
1 2 3 4 5 6 7 8 (NP)
RD48
5.6K
Rear IN CD38 RD25 RD27
CD35 1m50V 47K 33K
RD49 10m16V
2.2K
ENCODE
Fig. 15-13
[dB]
Response
f [Hz]
Response
f [Hz]
Fig. 15-14
120
13. DSP FRONT ADDITION CIRCUIT
Fig. 15-15 shows the front addition circuit for the surround
signal. In the DSP operation of this model, the surround
signal is added to the front channel to provide the surround
effect if rear speakers are not used.
In practice, the front addition surround signal output from
the DSP circuit is added to Lch with the phase non-inverted
and to Rch with the phase inverted.
RD01
20K QD02
5
Lch IN 7
Lch OUT Lch OUT
RD06
RD09 RD04 27K
16K 15K
Surround
REF
(L-R)
RD10
15K RD08
24K
RD07 9
RD05 15K 8
16K Rch OUT Rch OUT
Rch IN
10 QD02
Fig. 15-15
121
14. BUS CONVERTER 15. NEUTRAL BIAS
The bus converter receives I2C-bus data sent from the main To develop a neutral bias voltage for the OP amplifier, +B
microcomputer and converts them into DSP control data. (12V) is divided with resistors.
The data are transferred to the data input of the DSP.
To DSP (QD03)
+B
RD11 CD01
1K 100m16V
5 6 7 8
GND
DIN
SCI
AD
QD04
Fig. 15-17
RESET
SDA
SCL
Vcc
+5V
4 3 2 1
RD39 RD38
100 100
ICD03
16 pin
From main
microcomputer
Fig. 15-16
122
16. AUDIO OUTPUT AMPLIFIER (For Rear SP)
Vcc
C646 C650
100m25V 1000m35V
4 7
R640 C647 C641
6.8K 1000P 2.2m50V Ripple Filter Vcc
C652 R660
Rear INPUT 2 470m35V 1.5W(5W)
6
R641
1.8K R685
2.2W
SURROUND
1 SPEAKER
C645 C655 TERMINAL
R647 0.12m
22K 47m25V
3 Pre GND PW-GND 5
Mute
R644
100K
Fig. 15-18
123
17. TROUBLESHOOTING CHART
No sound.
NG
Is power supplied +5V, +12V lines? Check Power supply circuit.
OK
NG
Are input signals applied to 13 , 14 terminals? Check A/V SW output.
OK
NG
Are inputs applied to pins 14 , 8 of QD01? Check Input Buffer (QD01).
OK
NG
Do output pins L 10 , R 11 develop outputs? Check DSP front addition circuit (QD02).
OK
No rear sound.
OK
OK
NG
Do pin 7 and 8 of QD03 develop outputs? Check DSP (QD03) and DSP control data.
OK
NG
Does Sout 6 develop the output? Check LPF (QD06) and Dolby NR
circuit (QD07 & 02).
OK
124
SECTION XVI
FAILURE DIAGNOSIS PROCEDURES
125
1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES
No raster.
Check voltage
To "Start circuit diagnosis".
at pin 32 of 0501.
Check wafeform
at pin 23 of IC501.
NG NG
Check D431 Check voltage of Check and repair
cathode voltage. Audio + B line. power supply circuit.
OK OK
OK
OK
126
2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES
No vertical scanning
OK
OK
OK
OK
Replace Q302
127
3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT
Left-Right pin-cushion
distortion correction is
not carried out.
-27V OK
Parabora OK
waveform
Parabora OK
waveform
Parabora OK
waveform
128
4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES
129
5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE
With SW turned on, Higher than 24.1V. Check X-ray protection circuit, H output
check voltage across C471 circuit, X-ray protection detector circuit,
with oscilloscope. and repair.
• 125V line becomes over voltage, thyristor D862 comes in to failure, and when Q863 does not turn on, D888 is short-circuited
and intermittent oscillation occurs. To protect the circuit a double protection system is employed.
• When the overvoltage protection circuit is working. never turn on the power with the protection circuit disabled.
High voltage will be stepped up and secondary breakdown may occur.
130
6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES
* Diagnosis of video signal through VIDEO input is done by inner video signal SGV as well.
In this time, do not connect any cable to VIDEO 1.
131
(A) OSD AND PICTURE DO NOT APPEAR
NG
Check R920 (heater resistor) and
Check that heater or CRT lights.
power/def circuit.
OK
OK
NG
Check waveform of TP-47R, G, B. Check CRT and power/def
circuit.
OK
NG
Check Q907, Q910 and blanking
Check waveform of TP-46R, G, B.
circuit. (pow/def board)
OK
OK
OK
132
(B) OSD IS OK, PICTURE DOES NOT APPEAR
NG NG
NG
OK
Check waveform at pin 15 (Y1 output)
of Q501. Approx 1VP-P Check Q501.
NG
OK OK
OK
133
(B) OSD IS OK, PICTURE DOES NOT APPEAR (A/V CIRCUIT IS DEFECTIVE)
OK
Check waveform at pin 36 (Y-AV)
Check Q501. Go to (B).
or QV01. 2VP-P
NG
OK
Check waveform at pin 30 (Y-Comb) or QV01. Check QV01.
NG
OK
Check waveform at pin 38 (V-AV) or QV01. Check Comb filter. Go to (B).
NG
NG
Go to (D), (E)
134
(D) PICTURE OF ONLY VHF/UHF OF MAIN SCREEN
OK Check waveform OK
Check waveform at pin 7 Replace QV01
of H002. at pin 7 of QV01.
NG NG
Check/Replace QV40, QV41,
QV42, QV43.
NG
Check power voltage at pin 4 Check power circuit
of H002. 9V
OK
NG
OK
Replace H001.
135
(E) PICTURE ONLY VHF/UHF OF SUB SCREEN DOES NOT APPEAR(B) OSD IS
OK, PICTURE DOES NOT APPEAR
OK OK
Check waveform at pin 15 Replace QV01.
Check waveform
of HY01.
at pin 28 of QV01.
NG
NG
Check CV09,
RV12.
Check power voltage of HY01.
Pin9 9V
Pin7 5V
Pin2 32V
NG
Check power circuit.
OK
Replace HY01.
136
(F) NO COLOR (AFTER Q501)
OK
OK
OK
OK
OK
NG
Check Q501.
137
(G) NO COLOR (A/V, COMB)
OK NG
NG
Check Q501.
NG
OK
138