104.32us Every eight rClk cycles corresponds to a single period of tClk.

The rClk is controlled by the Baud Rate constant initialized in the beginning of the code. A single tClk cycle takes 5216 CLK cycles. tdReg gets the data from DBIN and holds it until the register is reset. The data from this register can be transmitted serially from tdxd. The purpose of tdSReg is to shift the data from tdReg out to be transmitted serially. The eight least significant bits of tdSReg are loaded with data to be sent. The other in tdSReg bits are Parity,Start and Stop Bits.

We start with sttCur == sttIdle. When TBEint goes low sstCur == sttTransfer. After the next clock cycle, sstCur == sttShift. It remains in the sstShift state until the counter reaches 12. Then sstCur == sttIdle.

PART B rdSReg is used to shift in the data being received and recomposing it to a 11 bit string. rdReg stores the 8 bit data once the entire 11 bit string is loaded into rdSReg. The dataCtr counts up to 11. It increments every clock cycle at the baud rate so that it increments once per incoming bit.

In the strIdle state, it will wait for both the RXD and FEint to be 0, then only it will go to the next state and ctRST will be set to 1. In the strEightDelay we wait for 8 periods of rClk so that data is sampled in the center of each bit. In strGetData ctRST and rShift will be set to one only when the counter value is 1111. And if the data counter value gets to 1010 it will go to the next state which is strCheckStop otherwise it will just continue to sample data. In the strCheckStop state everything is set to 0 except CE and then it goes back to the idle state strIdle.

23. The transmitter first generates the parity bit by checking whether the number of 1s in the data to be sent is even (0) or odd(1). It checks this by xoring all 4 pairs of bits, and then xoring these results. When this final answer is made, it is inverted to create the parity bit. Similarly the reciever checks the parity through a similar xoring process. It first determines whether the data is even or odd, and then it xors this result with the received parity bit. If the transmission was correct the result should be a 0.

25. A frame error occurs when serial data is read at the wrong point. We received a frame error when the data was 01101010100, which is not an actual value we simulated. Because of this, the frame error flag went high. 26. YES 27. The UART should still capture the data correctly because a 4% error is still within the acceptable limits of this particular UART and 11 bit transmissions. This is because the Bit period is approximately 104 us, but the max Baud error is -4.34 us off per cycle. This means that over 11 samples, the max time the sampling would be off by is about 47 us. This is well within the 104 us bound. 28. We observe that rShift becomes more and more out of sync with the input data. 29. We observe the same thing as before, however with such a big change the data becomes totally out of sync and totally unreliable within a few cycles.