UNIT I 8085 MICROPROCESSOR

MICROPROCESSOR

The microprocessor is a semiconductor device (integrated device) manufactured by the VLSI technique. It includes the AL ! register array and control circuit on a single chip. To perform a function or useful tas" #e have to form a system by using microprocessor as a $% it. A system designed using a microprocessor as its $% and interfacing memory! input and output devices to is called a microcomputer. The microprocessor based

system consists of microprocessor as $% ! semiconductor memories li"e &%'() and 'A)! input device! output device and interfacing devices are called peripherals. FUNDAMENTAL CONCEPTS Microcomputer* A programmable machine that processes binary data. There are three ma+or parts of a microcomputer system

)emory
$% ()icro %rocessor)

I.(

,igure *)icrocomputer - The CPU (Centr ! Proce""in# Unit$ #hich acts as the brain coordinating all Activities #ithin the computer i%e% The group of circuits that process data and provide control signals and timing. - The memor& unit #here the program instructions and data are temporarily stored - The I'O (Input'Output$ (e)ice" #hich allo# the computer to input information for %rocessing and then output the result. Today the $% microprocessor.
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circuitry has been reduced to ICs called the

EVOLUTION OF MICROPROCESSORS: *ener tion o+ microproce""or" )icroprocessors #ere categori/ed into five generations* first! second! third! fourth! and fifth generations. Their characteristics are described belo#* Fir"t,#ener tion The microprocessors that #ere introduced in 0120 to 0123 #ere referred to as the first generation systems. ,irst4generation microprocessors processed their instructions serially5they fetched the instruction! decoded it! then e6ecuted it. 7hen an instruction #as completed! the microprocessor updated the instruction pointer and fetched the ne6t instruction! performing this sequential drill for each instruction in turn. Secon( #ener tion 8y the late 0129s! enough transistors #ere available on the I$ to usher in the second generation of microprocessor sophistication* 0:4bit arithmetic and pipelined instruction processing. )otorola;s )$:<999 microprocessor! introduced in 0121! is an e6ample. Another e6ample is Intel;s <9<9. This generation is defined by overlapped fetch! decode! and e6ecute steps ($omputer 011:). As the first instruction is processed in the e6ecution unit! the second instruction is decoded and the third instruction is fetched. The distinction bet#een the first and second generation devices #as primarily the use of ne#er semiconductor technology to fabricate the chips. This ne# technology resulted in a five4fold increase in instruction! e6ecution! speed! and higher chip densities. Thir( #ener tion The third generation! introduced in 012<! #as represented by Intel;s <9<: and the =ilog =<999! #hich #ere 0:4bit processors #ith minicomputer4li"e performance. The third generation came about as I$ transistor counts approached 3>9!999. )otorola;s )$:<939! for e6ample! incorporated an on4chip cache for the first time and the depth of the pipeline increased to five or more stages. This generation of microprocessors #as different from the previous ones in that all ma+or #or"station manufacturers began developing their o#n 'IS$4 based microprocessor architectures ($omputer! 011:).

Fourth #ener tion As the #or"station companies converted from commercial microprocessors to in4house designs! microprocessors entered their fourth generation #ith designs surpassing a million transistors. Leading4edge microprocessors such as Intel;s <91:9$A and )otorola;s <<099 could issue and retire more than one instruction per cloc" cycle. Fi+th #ener tion )icroprocessors in their fifth generation! employed decoupled super scalar processing! and their design soon surpassed 09 million transistors. In this generation! %$s are a lo#4margin! high4volume4business dominated by a single microprocessor. Microproce""or" To( & Technology has been changing at a rapid pace. &veryday a ne# product is made to ma"e life a little easier. The computer plays a ma+or role in the lives of most people. It allo#s a person to do practically anything. The Internet enables the user to gain more "no#ledge at a much faster pace compared to researching through boo"s. The portion of the computer that allo#s it to do more #or" than a simple computer is the microprocessor. )icroprocessor has brought electronics into a ne# era and caused component manufacturers and end4users to rethin" the role of the computer. 7hat #as once a giant machine attended by specialists in a room of its o#n is no# a tiny device conveniently transparent to users of automobile! games! instruments! office equipment! and a large array of other products? ,rom their humble beginnings 3> years ago! microprocessors have proliferated into an astounding range of chips! po#ering devices ranging from telephones to supercomputers (%$ )aga/ine! 011:). Today! microprocessors for personal computers get #idespread attention5 and have enabled Intel to become the #orld@s largest semiconductor ma"er. In addition! embedded microprocessors are at the heart of a diverse range of devices that have become staples of affluent consumers #orld#ide. The impact of the microprocessor! ho#ever! goes far deeper than ne# and improved products. It is altering the structure of our society by changing ho# #e gather and use information! ho# #e communicate #ith one another! and ho# and #here #e #or". $omputer users #ant fast memory in their %$s! but most do not #ant to pay a premium for it.
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The " !ient +e ture" o+ 8085 Ap are* 0 3 D F > : 2 < 1 B It is a < bit microprocessor. B It is manufactured #ith C4)(S technology. B It has 0:4bit address bus and hence can address up to 30: E :>>D: bytes (:FG8) memory locations through A94A0>. B The first < lines of address bus and < lines of data bus are multiple6ed AH9 - AH2. B Hata bus is a group of < lines H9 - H2. B It supports e6ternal interrupt request. B A 0: bit program counter (%$) B A 0: bit stac" pointer (S%) B Si6 <4bit general purpose register arranged in pairs* 8$! H&! IL.

09 B It requires a signal J>V po#er supply and operates at D.3 )I= single phase cloc". 00 B It is enclosed #ith F9 pins HI% (Hual in line pac"age). 03 8085 ARC-ITECTURE The architecture of Intel <9<> consists of three main sections! arithmetic and logic unit! timing and control unit and several registers. The functional bloc" diagram of <9<> is sho#n in figure Contro! Unit Kenerates signals #ithin u% to carry out the instruction! #hich has been decoded. In reality causes certain connections bet#een bloc"s of the u% to be opened or closed! so that data goes #here it is required! and so that AL operations occur. Arithmetic Lo#ic Unit The AL performs the actual numerical and logic operation such as Ladd;! Lsubtract;! LACH;! L(';! etc. ses data from memory and from Accumulator to perform arithmetic. Al#ays stores result of operation in the accumulator. The AL performs the follo#ing arithmetic and logical operations. 0. Addition 3. Subtraction D. Logical ACH F. Logical (' >. Logical &M$L SIV& (' :. $omplement (logical C(T) 2. Increment (add 0) <. Hecrement (subtract 0)
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1. Left shift 09. $lear

The AL is the unit that manipulates the data. AL includes the accumulator! the temporary register! the arithmetic and logic circuits and flags. The AL performs the actual numerical and logic operation such as Ladd;! Lsubtract;! LACH;! L(';! etc. ses data from memory and from Accumulator to perform arithmetic. Al#ays stores result of operation in Accumulator.

REGISTERS The <9<>.<9<9A4programming model includes si6 registers! one accumulator! and one flag register! as sho#n in ,igure. In addition! it has t#o 0:4bit registers* the stac" pointer and the program counter. They are described briefly as follo#s.

Accumu! tor
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The accumulator is an <4bit register that is a part of arithmetic.logic unit (AL ). This register is used to store <4bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. The <9<>.<9<9A has si6 general4purpose registers to store <4bit dataN these are identified as 8!$!H!&!I! and L as sho#n in the figure. They can be combined as register pairs 4 8$! H&! and IL 4 to perform some 0:4bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions. F! #" The AL includes five flip4flops! #hich are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called =ero(=)! $arry ($O)! Sign (S)! %arity (%)! and Au6iliary $arry (A$) flagsN they are listed in the Table and their bit positions in the flag register are sho#n in the ,igure belo#. The most commonly used flags are =ero! $arry! and Sign. The microprocessor uses these flags to test data conditions. ,or e6ample! after an addition of t#o numbers! if the sum in the accumulator id larger than eight bits! the flip4flop uses to indicate a carry 44 called the $arry flag ($O) - is set to one. 7hen an arithmetic operation results in /ero! the flip4flop called the =ero(=) flag is set to one.

The ,igure sho#s an <4bit register! called the flag register! ad+acent to the accumulator. Io#ever! it is not used as a registerN five bit positions out of eight are used to store the outputs of the five flip4flops. The flags are stored in the <4bit register so that the programmer can e6amine these flags (data conditions) by accessing the register through an instruction. These flags have critical importance in the decision4ma"ing process of the microprocessor. The

conditions (set or reset) of the flags are tested through the soft#are instructions. ,or e6ample! the instruction
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P$ (Pump on $arry) is implemented to change the sequence of a program #hen $O flag is set. The thorough understanding of flag is essential in #riting assembly language programs. Pro#r m Counter (PC$ This 0:4bit register deals #ith sequencing the e6ecution of instructions. This register is a memory pointer. )emory locations have 0:4bit addresses! and that is #hy this is a 0:4bit register. The microprocessor uses this register to sequence the e6ecution of the instructions. The function of the program counter is to point to the memory address from #hich the ne6t byte is to be fetched. 7hen a byte (machine code) is being fetched! the program counter is incremented by one to point to the ne6t memory location St c. Pointer (SP$ The stac" pointer is also a 0:4bit register used as a memory pointer. It points to a memory location in '.7 memory! called the stac". The beginning of the stac" is defined by loading 0:4bit address in the stac" pointer. In"truction Re#i"ter'Deco(er Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to e6ecution. Hecoder then ta"es instruction and Ldecodes; or interprets the instruction. Hecoded instruction then passed to ne6t stage. Memor& A((re"" Re#i"ter Iolds address! received from %$! of ne6t program instruction. ,eeds the address bus #ith addresses of location of the program under e6ecution. Contro! *ener tor Kenerates signals #ithin u% to carry out the instruction #hich has been decoded. In reality causes certain connections bet#een bloc"s of the u% to be opened or closed! so that data goes #here it is required! and so that AL operations occur. Re#i"ter Se!ector
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This bloc" controls the use of the register stac" in the e6ample. Pust a logic circuit #hich s#itches bet#een different registers in the set #ill receive instructions from $ontrol nit. *ener ! Purpo"e Re#i"ter" )icroprocessor requires e6tra registers for versatility. It can be used to store additional data during a program. )ore comple6 processors may have a variety of differently named registers. 8085 System Bus -ADDRESS AND DATA BUSSES Typical system uses a number of busses! collection of #ires! #hich transmit binary numbers! one bit per #ire. A typical microprocessor communicates #ith memory and other devices (input and output) using three busses* Address 8us! Hata 8us and $ontrol 8us. A((re"" /u" (ne #ire for each bit! therefore 0: bits E 0: #ires. 8inary number carried alerts memory to Lopen; the designated bo6. Hata (binary) can then be put in or ta"en out.The Address 8us consists of 0: #ires! therefore 0: bits. Its Q#idthQ is 0: bits. A 0: bit binary number allo#s 30: different numbers! or D3999 different numbers! ie 9999999999999999 up to 0000000000000000. 8ecause memory consists of bo6es! each #ith a unique address! the si/e of the address bus determines the si/e of memory! #hich can be used. To communicate #ith memory the microprocessor sends an address on the address bus! e.g. 9999999999999900 (D in decimal)! to the memory. The memory the selects bo6 number D for reading or #riting data. Address bus is unidirectional! ie numbers only sent from microprocessor to memory! not other #ay. D t /u" Hata 8us carries Ldata;! in binary form! bet#een A% and other e6ternal units! such as memory. Typical si/e is < or 0: bits. Si/e determined by si/e of bo6es in memory and A% si/e helps determine performance of A%. The Hata 8us typically consists of < #ires. Therefore! 3< combinations of binary digits. Hata bus used to transmit QdataQ! ie information! results of arithmetic! etc! bet#een memory and the microprocessor. 8us is bi4 directional. Si/e of the data bus determines #hat arithmetic can be done. If only < bits #ide then largest number is 00000000 (3>> in decimal). Therefore! larger number have to be bro"en do#n into chun"s of 3>>. This slo#s microprocessor. Hata 8us also carries instructions from memory to the microprocessor. Si/e of the bus therefore limits the number of possible instructions to 3>:! each specified by a separate number. Contro! /u"
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$ontrol 8us are various lines #hich have specific functions for coordinating and controlling microprocessor operations. &g* 'ead.Cot7rite line! single binary digit. $ontrol #hether memory is being L#ritten to; (data stored in mem) or Lread from; (data ta"en out of mem) 0 E 'ead! 9 E 7rite. )ay also include cloc" line(s) for timing.synchroni/ing! Linterrupts;! Lreset; etc. Typically A% has 09 control lines. The $ontrol 8us carries control signals partly unidirectional! partly bi4directional. $ontrol signals are things li"e Qread or #riteQ. This tells memory that #e are either re (in# +rom a location! specified on the address bus! or 0ritin# to a location specified. Various other signals to control and coordinate the operation of the system. )odern day microprocessors! li"e <9D<:! <9F<: have much larger busses. Typically 0: or D3 bit busses! #hich allo# larger number of instructions! more memory location! and faster arithmetic. )icrocontrollers organi/ed along same lines! e6cept* because microcontrollers have memory etc inside the chip! the busses may all be internal. In the microprocessor the three busses are e6ternal to the chip (e6cept for the internal data bus). In case of e6ternal busses! the chip connects to the busses via buffers! #hich are simply an electronic connection bet#een e6ternal bus and the internal data bus. Pin De"cription

A8 , A15 (Output 2 St te$ Address 8usN The most significant < bits of the memory address or the < bits of the I.9 address!D stated during Iold and Ialt modes. AD0 , AD3 (Input'Output 2"t te$
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)ultiple6ed Address.Hata 8usN Lo#er < bits of the memory address (or I.9 address) appear on the bus during the first cloc" cycle of a machine state. It then becomes the data bus during the second and third cloc" cycles. D stated during Iold and Ialt modes. ALE (Output$ Address Latch &nable* It occurs during the first cloc" cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of AL& is set to guarantee setup and hold times for the address information. AL& can also be used to strobe the status information. AL& is never Dstated. TIMING AND CONTROL SIGNALS SO4 S1 (Output$ Hata 8us Status. &ncoded status of the bus cycle* S0 ( 9 0 0 S9 ( 0 9 0 IALT 7'IT& '&AH ,&T$I

S0 can be used as an advanced '.7 status. RD5 (Output 2"t te$ '&AH indicates the selected memory or 0.9 device is to be read and that the Hata 8us is available for the data transfer. 6R5 (Output 2"t te$ 7'IT& indicates the data on the Hata 8us is to be #ritten into the selected memory or 0.9 location. Hata is set up at the trailing edge of 7'. Dstated during Iold and Ialt modes.

READ7 (Input$ If 'eady is high during a read or #rite cycle! it indicates that the memory or peripheral is ready to send or receive data. If 'eady is lo#! the $% cycle. #ill #ait for 'eady to go high before completing the read or #rite

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-OLD (Input$ I(LH indicates that another )aster is requesting the use of the Address and Hata 8uses. The $% ! upon receiving the Iold request. It #ill relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Iold is removed. 7hen the Iold is ac"no#ledged! the Address! Hata! 'H! 7'! and I(.) lines are Dstated. -LDA (Output$ I(LH A$GC(7L&HK& indicates that the $% the buses one half cloc" cycle after ILHA goes lo#. RESET IN5 (Input$ 'eset sets the %rogram $ounter to /ero and resets the Interrupt &nable and ILHA flipflops. Cone of the other flags or registers (e6cept the instruction register) are affected The $% long as 'eset is applied. RESET OUT (Output$ Indicates $% processor cloc". CL8 (Output$ $loc" (utput for use as a system cloc" #hen a crystal or '. $ net#or" is used as an input to the $% . The period of $LG is t#ice the M0! M3 input period. IO'M5 (Output$ I(.) indicates #hether the 'ead.7rite is to memory or l.( Tristated during Iold and Ialt modes. is being reset. It can be used as a system '&S&T. The signal is synchroni/ed to the is held in the reset condition as has received the Iold request and that it #ill relinquish the buses in the ne6t cloc" cycle. ILHA goes lo# after the Iold request is removed. The $% ta"es

INTERUPTS9 INTR (Input$ ICT&'' %T '&R &ST is used as a general purpose interrupt. It is sampled only during the ne6t to the last cloc" cycle of the instruction. If it is active! the %rogram $ounter (%$) #ill be inhibited from incrementing and an ICTA #ill be issued. Huring this cycle a '&STA'T or $ALL instruction can be inserted
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to +ump to the interrupt service routine. The ICT' is enabled and disabled by soft#are. It is disabled by 'eset and immediately after an interrupt is accepted. INTA 5 (Output$ ICT&'' %T A$GC(7L&HK& is used instead of (and has the same timing as) 'H during the Instruction cycle after an ICT' is accepted. It can be used to activate the <3>1 Interrupt chip or some other interrupt port. RST 5%5 RST :%5 , (Input"$ RST 3%5 '&STA'T ICT&'' %TS These three inputs have the same timing as I CT' e6cept they cause an internal '&STA'T to be automatically inserted. 'ST 2.> SS Iighest %riority 'ST :.> 'ST >.> o Lo#est %riority The priority of these interrupts is ordered as sho#n above. These interrupts have a higher priority than the ICT'. TRAP (Input$ Trap interrupt is a nonmas"able restart interrupt. It is recogni/ed at the same time as ICT'. It is unaffected by any mas" or Interrupt &nable. It has the highest priority of any interrupt. ;14 ;< (Input$ $rystal or '.$ net#or" connections to set the internal cloc" generator M0 can also be an e6ternal cloc" input instead of a crystal. The input frequency is divided by 3 to give the internal operating frequency. SERIAL INPUT AND OUTPUT SID (Input$ Serial input data line The data on this line is loaded into accumulator bit 2 #henever a 'I) instruction is e6ecuted. SOD (output$ Serial output data line. The output S(H is set or reset as specified by the SI) instruction. =cc , J> volt supply. ="" , Kround 'eference. INSTRUCTION FORMAT
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An in"truction is a command to the microprocessor to perform a given tas" on a specified data. &ach instruction has t#o parts* one is tas" to be performed! called the oper tion co(e (opcode)! and the second is the data to be operated on! called the oper n(% The operand (or data) can be specified in various #ays. It may include <4bit (or 0:4bit ) data! an internal register! a memory location! or <4bit (or 0:4bit) address. In some instructions! the operand is implicit. In"truction 0or( "i>e The <9<> instruction set is classified into the follo#ing three groups according to #ord si/e* 1% (ne4#ord or 04byte instructions <% T#o4#ord or 34byte instructions 2% Three4#ord or D4byte instructions In the <9<>! QbyteQ and Q#ordQ are synonymous because it is an <4bit microprocessor. Io#ever! instructions are commonly referred to in terms of bytes rather than #ords. One,/&te In"truction" A 04byte instruction includes the opcode and operand in the same byte. (perand(s) are internal register and are coded into the instruction. ,or e6ample*

These instructions are 04byte instructions performing three different tas"s. In the first instruction! both operand registers are specified. In the second instruction! the operand 8 is specified and the accumulator is assumed. Similarly! in the third instruction! the accumulator is assumed to be the implicit operand. These instructions are stored in <4 bit binary format in memoryN each requires one memory location.

)(V rd! rs rd T44 rs copies contents of rs into rd. $oded as 90 ddd sss #here ddd is a code for one of the 2 general registers #hich is the destination of the data! sss is the code of the source register. E? mp!e* )(V A!8 $oded as 90000999 E 2<I E 029 octal (octal #as used e6tensively in instruction design of such processors). AHH r
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A T44 A J r T0o,/&te In"truction" In a t#o4byte instruction! the first byte specifies the operation code and the second byte specifies the operand. Source operand is a data byte immediately follo#ing the opcode. ,or e6ample*

Assume that the data byte is D3I. The assembly language instruction is #ritten as

The instruction #ould require t#o memory locations to store in memory. )VI r!data r T44 data E? mp!e9 )VI A! D9I coded as D&I D9I as t#o contiguous bytes. This is an e6ample of immediate addressing. AHI data A T44 A J data ( T port 9900 0009 HATA #here port is an <4bit device address. (%ort) T44 A. Since the byte is not the data but points directly to #here it is located this is called direct addressing. Three,/&te In"truction" In a three4byte instruction! the first byte specifies the opcode! and the follo#ing t#o bytes specify the 0:4bit address. Cote that the second byte is the lo#4order address and the third byte is the high4order address. opcode J data byte J data byte ,or e6ample*

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This instruction #ould require three memory locations to store in memory. Three byte instructions 4 opcode J data byte J data byte LMI rp! data0: rp is one of the pairs of registers 8$! H&! IL used as 0:4bit registers. The t#o data bytes are 0:4bit data in L I order of significance. rp T44 data0: E? mp!e9 LMI I!9>39I coded as 30I 39I >9I in three bytes. This is also immediate addressing. LHA addr A T44 (addr) Addr is a 0:4bit address in L I order. &6ample* LHA 30DFI coded as DAI DFI 30I. This is also an e6ample of direct addressing. INSTRUCTION CLASSIFICATION9 Instructions have been classified into the follo#ing groups* 0. Hata Transfer Kroup 3. Arithmetic Kroup D. Logical Kroup F. 8ranch $ontrol Kroup >. I.( and )achine $ontrol Kroup

D t Tr n"+er Croup9 The data transfer instructions move data bet#een registers or bet#een memory and registers. )(V )VI )ove )ove Immediate LHA Load Accumulator Hirectly from )emory
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STA

Store Accumulator Hirectly in )emory Load I U L 'egisters Hirectly from )emory Store I U L 'egisters Hirectly in )emory

LILH SILH

An @M@ in the name of a data transfer instruction implies that it deals #ith a register pair (0:4bits)N LMI Load 'egister %air #ith Immediate data Load Accumulator from Address in 'egister %air Store Accumulator in Address in 'egister %air &6change I U L #ith H U & &6change Top of Stac" #ith I U L

LHAM STAM M$IK MTIL

Arithmetic *roup9 The arithmetic instructions add! subtract! increment! or decrement data in registers or memory. AHH AHI Add to Accumulator Add Immediate Hata to Accumulator Add to Accumulator sing $arry ,lag Add Immediate data to Accumulator sing $arry Subtract from Accumulator S I Subtract Immediate Hata from Accumulator Subtract from Accumulator sing 8orro# ($arry) ,lag Subtract Immediate from Accumulator sing 8orro# ($arry) ,lag Increment Specified 8yte by (ne

AH$ A$I S 8 S88 S8I IC'

H$' ICM

Hecrement Specified 8yte by (ne Increment 'egister %air by (ne

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H$M

Hecrement 'egister %air by (ne

HAH Houble 'egister AddN Add $ontent of 'egister

%air to I U L 'egister %air Logical Kroup* This group performs logical (8oolean) operations on data in registers and memory and on condition flags. The logical ACH! ('! and &6clusive (' instructions enable you to set specific bits in the accumulator (C or (,,. ACA ACI Logical ACH #ith Accumulator Logical ACH #ith Accumulator sing Immediate Hata Logical (' #ith Accumulator Logical (' #ith Accumulator sing Immediate Hata &6clusive Logical (' #ith Accumulator &6clusive (' sing Immediate Hata

('A ('

M'A M'I

The $ompare instructions compare the content of an <4bit value #ith the contents of the accumulatorN $)% $%I $ompare $ompare sing Immediate Hata

The rotate instructions shift the contents of the accumulator one bit position to the left or right* 'L$ 'otate Accumulator Left ''$ 'AL 'otate Accumulator 'ight 'otate Left Through $arry 'otate 'ight Through $arry

'A'

$omplement and carry flag instructions* $)A $omplement Accumulator

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$)$

$omplement $arry ,lag ST$ Set $arry ,lag

/r nch *roup9 The branching instructions alter normal sequential program flo#! either unconditionally or conditionally. The unconditional branching instructions are as follo#s* P)% Pump $all 'eturn

$ALL '&T

$onditional branching instructions e6amine the status of one of four condition flags to determine #hether the specified branch is to be e6ecuted. The conditions that may be specified are as follo#s* C= = C$ $ %( %& ) Cot =ero (= E 9) =ero (= E 0) Co $arry ($ E 9) $arry ($ E 0) %arity (dd (% E 9) %arity &ven (% E 0) % %lus (S E 9) )inus (S E 0)

Thus! the conditional branching instructions are specified as follo#s* Pumps $alls 'eturns P$ $$ '$ ($arry) PC$ $C$ 'C$ (Co $arry)

P= $= '= (=ero)
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PC= $C= 'C= (Cot =ero) P% $% '% (%lus) P) $) ') ()inus) P%& $%& '%& (%arity &ven) P%9 $%( '%( (%arity (dd) T#o other instructions can affect a branch by replacing the contents or the program counter* %$IL 'ST )ove I U L to %rogram $ounter Special 'estart Instruction sed #ith Interrupts

St c. I'O4 n( M chine Contro! In"truction"9 The follo#ing instructions affect the St c. and.or Stac" %ointer* % SI MTIL S%IL %ush T#o bytes of Hata onto the Stac" %(% %op T#o 8ytes of Hata off the Stac" &6change Top of Stac" #ith I U L )ove content of I U L to Stac" %ointer

The I'0 in"truction" are as follo#s* IC Initiate Input (peration Initiate (utput (peration

( T

The M chine Contro! instructions are as follo#s* &I HI ILT C(% &nable Interrupt System Hisable Interrupt System Ialt Co (peration

ADDRESSING MODES The various formats for specifying operands are called the AHH'&SSICK )(H&S. ,or <9<>! they are* 0. Immediate addressing. 3. 'egister addressing. D. Hirect addressing.
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F. Indirect addressing. Imme(i te ((re""in# Hata is present in the instruction. Load the immediate data to the destination provided. &6ample* )VI '!data Re#i"ter ((re""in# Hata is provided through the registers. &6ample* )(V 'd! 's Direct ((re""in# sed to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 99I and store them into the accumulator or Send the data from the accumulator to the port 90I. &6ample* IC 99I or ( T 90I In(irect A((re""in# This means that the &ffective Address is calculated by the processor. And the contents of the address (and the one follo#ing) is used to form a second address. The second address is #here the data is stored. Cote that this requires several memory accessesN t#o accesses to retrieve the 0:4bit address and a further access (or accesses) to retrieve the data #hich is to be loaded into the register. ASSEMBLY LANGUAGE PROGRAMMING To perform addition of t#o < bit numbers using <9<>. ALK('ITI)* 0) Start the program by loading the first data into Accumulator. 3) )ove the data to a register (8 register). D) Ket the second data and load into Accumulator.F) Add the t#o register contents. >) $hec" for carry. :) Store the value of sum and carry in memory location. 2) Terminate the program.

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%'(K'A)* )VI $! 99 LHA F0>9 )(V8! A LHAF0>0 AHH8 PC$ L((% IC' $ L((%* STA F0>3 )(V A! $ STA F0>D ILT (8S&'VATI(C* Input* <9 (F0>9) <9 (F3>0) (utput* 99 (F0>3) 90 (F0>D) %rogram3* To perform the subtraction of t#o < bit numbers using <9<>. ALK('ITI)* 0. Start the program by loading the first data into Accumulator. 3. )ove the data to a register (8 register). D. Ket the second data and load into Accumulator. F. Subtract the t#o register contents. >. $hec" for carry. :. If carry is present ta"e 3;s complement of Accumulator. 2. Store the value of borro# in memory location. <. Store the difference value (present in Accumulator) to a memory location and terminate the program. %'(K'A)* )VI $! 99 Initiali/e $ to 99
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Initiali/e $ register to 99 Load the value to Accumulator. )ove the content of Accumulator to 8 register. Load the value to Accumulator. Add the value of register 8 to A Pump on no carry. Increment value of register $ Store the value of Accumulator (S )). )ove content of register $ to Acc. Store the value of Accumulator ($A''O) Ialt the program.

LHA F0>9 )(V 8! A LHA F0>0 S 88 PC$ L((% $)A IC' IC' $ $L((%* STA F0>3 )(V A! $ STA F0>D ILT (8S&'VATI(C* Input* 9: (F0>9) 93 (F3>0)

Load the value to Acc. )ove the content of Acc to 8 register. Load the value to Acc.

Pump on no carry. $omplement Accumulator contents. A Increment value in Accumulator. Increment value in register Store the value of A4reg to memory address. )ove contents of register $ to Accumulator. Store the value of Accumulator memory address. Terminate the program.

(utput*

9F (F0>3) 90 (F0>D)

%rogramD* To perform the multiplication of t#o < bit numbers using <9<>. ALK('ITI)*0) location. Start the program by loading IL register pair #ith address of memory

3) )ove the data to a register (8 register).D) Ket the second data and load into Accumulator. F) Add the t#o register contents. >) $hec" for carry. :) Increment the value of carry. 2) $hec" #hether repeated addition is over and store the value of product and carry in memory location. <) Terminate the program. %'(K'A)* )VI H! 99 )VI A! 99 LMI I! F0>9
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Initiali/e register H to 99 Initiali/e Accumulator content to 99

)(V 8! ) ICM I

Ket the first number in 8 4 reg

)(V $! ) L((%* AHH PC$ IC' C&MT* H$' PC= 8 C&MT H $ L((%

Ket the second number in $4 reg. Add content of A 4 reg to register 8. Pump on no carry to C&MT. Increment content of register H Hecrement content of register $. Pump on no /ero to address Store the result in )emory

STA F0>3 )(V A! H

STA F0>D ILT (8S&'VATI(C* Input* ,, (F0>9) ,, (F0>0)

Store the )S8 of result in )emory Terminate the program.

(utput*

90 (F0>3) ,& (F0>D)

%rogram3 * To perform the division of t#o < bit numbers using <9<>. ALK('ITI)*0) Start the program by loading IL register pair #ith address of memory location. 3) )ove the data to a register(8 register). D) Ket the second data and load into Accumulator. F) $ompare the t#o numbers to chec" for carry. >) Subtract the t#o numbers. :) Increment the value of carry. 2) $hec" #hether repeated subtraction is over and store the value of product and carry in memory location. <) Terminate the program. %'(K'A)* LMI I! F0>9 )(V 8! ) )VI $! 99 Ket the dividend in 8 4reg. $lear $ 4 reg for qoutient
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ICM I )(V A! ) C&MT* $)% 8 P$ L((% S 88 IC' $ P)% C&MT L((%* STA F0>3 )(V A! $ STA F0>D ILT (8S&'VATI(C* Input* ,, (F0>9) ,, (F3>0) (utput* 90 (F0>3) 4444 'emainder ,& (F0>D) 4444 Ruotient Store the quotient in memory Terminate the program. Ket the divisor in A4 reg. $ompare A 4 reg #ith register 8. Pump on carry to L((% Subtract A 4 reg from 84reg. Increment content ofregister $. Pump to C&MT Store the remainder in )emory

%rogram >* To find the largest number in an array of data using <9<> instruction set. ALK('ITI)* 0) Load the address of the first element of the array in IL pair 3) )ove the count to 8 4 reg. D) Increment the pointer F) Ket the first data in A 4 reg. >) Hecrement the count. :) Increment the pointer 2) $ompare the content of memory addressed by IL pair #ith that of A 4 reg. <) If $arry E 9! go to step 09 or if $arry E 0 go to step 1 1) )ove the content of memory addressed by IL to A 4 reg. 09) 09) Hecrement the count
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00) $hec" for =ero of the count. If =, E 9! go to step :! or if =, E 0 go to ne6t step. 03) Store the largest data in memory. 0D) Terminate the program. %'(K'A)* LMI I!F399 )(V 8!) ICM I )(V A!) H$' 8 L((%* ICM I $)% ) If A4 reg V AI&AH PC$ AI&AH )(V A!) AI&AH* H$' 8 PC= L((% STA FD99 ILT (8S&'VATI(C* Input* 9F (F399) 44444Array Si/e 9A (F390) ,0 (F393) 0, (F39D) ,& (F39F) (utput* ,& (FD99) 'epeat comparisons till count E 9 Store the largest value at FD99 Set the ne# value as largest ) go to Set 0st element as largest data Hecrement the count Set pointer for array Load the $ount

STAC S AND SUBROUTINES It is a part of memory! reserved in 'A)! used to temporarily store information during e6ecution of program.
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Starting address of stac" is loaded in WStac" %ointer (S%)X (a 0:4bit register). The address pointed to by S% is "no#n as WTop of Stac"X! #hich is al#ays an empty memory location.

St c. Initi !i> tion Stac" can be defined any#here in 'A). 8ut generally it initiali/ed from highest (end) address of 'A) to avoid any data loss.

Si>e o+ St c. Memor& Theoretically there is no limitation on the si/e of stac" memory. %ractically the si/e of stac" memory is limited to the availability of free 'A). As 'A) is used to store temporarily program and data during e6ecution! hence only free 'A) can be used as stac".

Storin# D t on St c. Stac" is Last4In4,irst4(ut (LI,() type of memory. 7hen information is stored on stac"! the Stac" %ointer register decrements to point to lo#er empty address. 7hen information is read from stac"! the Stac" %ointer register increments to point to higher empty address.

A() nt #e" o+ St c. Address is al#ays in Stac" %ointer! need not be part of instruction! therefore! stac" access is al#ays faster. Stac" instructions are short #ith only one operand. sed to save important data before branch instruction e.g. +ump or interrupt instruction

MEMORY AND I!O INTERFACING An interface is a concept that refers to a point of interaction bet#een components! and is applicable at the level of both hard#are and soft#are.
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This allo#s a component! (such as a graphics card or an Internet bro#ser)! to function independently #hile using interfaces to communicate #ith other components via an input.output system and an associated protocol. E? mp!e9

8085 Inter+ cin# Pin"9

Address 8us sed to address memory U I.( devices

Hata 8us sed to transfer instructions and data

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-i#her Or(er A((re"" /u"9 The higher order address bus is a unidirectional bus. It carries most significant <4bits of a 0:4bit address of memory or I.( device. Address remains on lines as long operation is not completed.

Lo0er Or(er A((re""'D t /u"9 This bus is bidirectional and #or"s on time division multiple6ing bet#een address and data. Huring first cloc" cycle! it serves as a least significant <4bit of memory. I( address. ,or second and third cloc" cycles it acts as data bus and carries data.

Demu!tip!e?in# A((re""'D t Line"9 <9<> identifies a memory location #ith its 0: address lines! (AH9 to AH2) U (A< to A0>) <9<> performs data transfer using its data lines! AH9 to AH2 Lo#er order address bus U Hata bus are multiple6ed on same lines i.e. AH9 to AH2. Hemultiple6ing refers to separating Address U Hata signals for read.#rite operations.

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Memor& Inter+ ce9 The memory is made up of semiconductor material used to store the programs and data. The types of memory is! %rimary or main memory Secondary memory Prim r& Memor&9 'A) and '() are e6amples of this type of memory. )icroprocessor uses it in storing a program temporarily (commonly called loading) and e6ecuting a program. Ience the speed of this type of memory should be fast.

Secon( r& memor& These are used for bul" storage of data and information. The main e6amples include ,loppy! Iard His"! $H4'()! )agnetic Tape etc. Slo#er and Sequential Access Cature. non4volatile nature.
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Memor& Chip9

8085 Inter+ cin# 0ith Memor& chip"9

There needs to be a lot of interaction bet#een the microprocessor and the memory for the e6change of information during program e6ecution. )emory has its requirements on control signals and their timing. The microprocessor has its requirements as #ell. The interfacing operation is simply the matching of these requirements.

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The #ay of interfacing the above t#o chips to the microprocessor is the same. Io#ever! the '() does not have a 7' signal. Accessing memory can be summari/ed into the follo#ing three steps* 0. Select the chip. 3. Identify the memory register. D. &nable the appropriate buffer. Translating this to microprocessor domain* The microprocessor places a 0:4bit address on the address bus. %art of the address bus #ill select the chip and the other part #ill go through the address decoder to select the register. The signals I(.) and 'H combined indicate that a memory read operation is in progress. The )&)' signal can be used to enable the 'H line on the memory chip. The result of Laddress decoding; is the identification of a register for a given address. A large part of the address bus is usually connected directly to the address inputs of the memory chip. This portion is decoded internally #ithin the chip. 7hat concerns us is the other part that must be decoded e6ternally to select the chip. This can be done either using logic gates or a decoder.

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There are t#o types of address decoding techniques &6haustive Hecoding %artial Hecoding

E?h u"ti)e Deco(in#9 In this type of scheme all the 0: bits of the <9<> address bus are used to select a particular location in memory chip.

Advantages* $omplete Address tili/ation &ase in ,uture &6pansion Co 8us $ontention! as all addresses are unique.

Hisadvantages Increased hard#are and cost. Speed is less due to increased delay.

P rti ! Deco(in#*
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In this scheme! minimum number of address lines is used as required to select a memory location in chip. Advantages* Simple! $heap and ,ast.

Hisadvantages* nutili/ed space U fold bac" (multiple mapping).

8us $ontention. Hifficult future e6pansion. Inter+ cin# I'O De)ice"9 sing I.( devices data can be transferred bet#een the microprocessor and the outside #orld. This can be done in groups of < bits using the entire data bus. This is called parallel I.(. The other method is serial I.( #here one bit is transferred at a time using the SIH and S(H pins on the )icroprocessor.

T&pe" o+ P r !!e! Inter+ ce9 There are t#o #ays to interface <9<> #ith I.( devices in parallel data transfer mode* )emory )apped I( I( )apped I( Memor& M ppe( IO9 It considers them li"e any other memory location. They are assigned a 0:4bit address #ithin the address range of the <9<>. The e6change of data #ith these devices follo#s the transfer of data #ith memory. The user uses the same instructions used for memory. IO M ppe( IO9 It treats them separately from memory. I.( devices are assigned a Wport numberX #ithin the <4bit address range of 99I to ,,I. The user in this case #ould access these devices using the IC and ( T instructions only.

IO MAPPED IO MEMOR7 MAPPED IO

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I( is treated as memory. 0:4bit addressing. )ore Hecoder Iard#are. $an address 30:E:F" locations. Less memory is available )emory Instructions are used. )emory control signals are used. Arithmetic and logic operations can be performed on data. Hata transfer b.# register and I(.

I( is treated I(. <4 bit addressing. Less Hecoder Iard#are. $an address 3<E3>: locations. 7hole memory address space is available. Special Instructions are used li"e IC! ( T. Special control signals are used. Arithmetic and logic operations can not be performed on data. Hata transfer b.# accumulator and I(.

The inter+ cin# o+ output (e)ice"9 (utput devices are usually slo#. Also! the output is usually e6pected to continue appearing on the output device for a long period of time. Kiven that the data #ill only be present on the data lines for a very short period (microseconds)! it has to be latched e6ternally. To do this the e6ternal latch should be enabled #hen the port;s address is present on the address bus! the I(.) signal is set high and 7' is set lo#. The resulting signal #ould be active #hen the output device is being accessed by the microprocessor. Hecoding the address bus (for memory4mapped devices) follo#s the same techniques discussed in interfacing memory.

Inter+ cin# o+ Input De)ice"9 The basic concepts are similar to interfacing of output devices. The address lines are decoded to generate a signal that is active #hen the particular port is being accessed. An I('H signal is generated by combining the I(.) and the 'H signals from the microprocessor.
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A tri4state buffer is used to connect the input device to the data bus. The control (&nable) for these buffers is connected to the result of combining the address signal and the signal I('H.

1. DESIGN A MEMORY MAPPING CIRCUIT OF 2K OF RAM AND 2 ROM SIZES OF 4K. Solution:

To design 3G of 'A)! <9<> needs 00 (A094A9) address lines for the register select.

3n E 3GN nE 00. To design FG of '()! <9<> needs 03 (A004A9) address lines for the register select. 3n E FGN nE 03. The memory mapping is sho#n belo#* To interface these memory devices #ith <9<> using decoder! A0>! A0F! A0D of the higher order address bus are used as the input lines for the decoder and the corresponding output lines to #hich the memory device connected acts as the chip select signal. The output line (o! (0! (3 are connected to the memory devices ('A) I! '() I! '() II) respectively. The control signals are given to each of the memory device as sho#n in figure. The lo#er order address bus is given to the latch signal and it is de4multiple6ed. The output of the latch is the lo# order address lines are used for the register select. The data lines are connected as sho#n in figure.

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A03 of the higher address line is connected to one of the enable line (&0) of the decoder. &D connected to J>V and the other is connected to the ground.

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