GROUP 8 FINAL PROJECT, FALL 2004, EECS 413, UNIVERSITY OF MICHIGAN, ANN ARBOR.
A Low-Voltage High Gain CMOS Op Amp for
SC Circuits with 1GHz Bandwidth
Chun C. Lee, Jason May and Alex Grichener
Abstract—This paper discusses the design of high gain, high
bandwidth, fully differential CMOS Op-amp in a low voltage
(VDD = 2.0V) 0.25µm CMOS process. This Op-amp is ideally
suited for switch-capacitor circuits and simulations show a unity
gain bandwidth of 1GHz with 1pF load capacitor and a DC gain
of more than 75dB. The phase margin is around 65o with a
feedback factor of 1. The circuit topology is a single-stage folded
cascode structure with regulated cascodes for gain boosting.
Index Terms—Common mode feedback (CMFB), folded
cascode, regulated cascode, telescopic amplifier.
I. INTRODUCTION
A S CMOS process technologies scale down, so do the
supply voltages. These trends in CMOS processes are
driven by the needs of digital designs. While low supply
voltages make analog design more difficult, it is important to
keep up with the trends because mixed-signal and SoC
designs require integration of both digital and analog
electronics [1].
Switch-capacitor filters are widely used analog building
blocks, and are essential in A/D converters and sample-and-
hold amplifiers. They are implemented using op-amps, and
their accuracy and speed are in turn dependent on the gain and
bandwidth of the op-amp [2]. The opamps used in such
applications are designed to drive capacitive loads only, and
are unfit for driving resistive loads.
Building CMOS op-amps with high gain and high
bandwidth at a low supply voltage is a difficult task. Various
op-amp structures are known, and some of the popular ones
[2] are: (i) Telescopic (ii) Folded cascode (iii) Regulated
cascode (iv) 2-stage op-amp. Fig. 1 shows these various
Manuscript received December 14, 2004. This work was done for the
fulfillment of credit requirements of course EECS 413 at EECS Department,
University of Michigan, Ann Arbor.
Chun C. Lee is a first year graduate student majoring in EE: Circuits at the
EECS Department of University of Michigan, Ann Arbor. Phone: 734-644-
3001; e-mail: leechun@umich.edu.
Jason W. May is a senior majoring in EE at the EECS department of the
University of Michigan, Ann Arbor. Phone: 719-661-2969; email
jwmay@umich.edu
Alex Grichener is a first year graduate student majoring in EE: RF Circuits
and Applied EM at the EECS Department of University of Michigan, Ann
Arbor. Phone: 763-544-2500; email: agrichen@umich.edu.
topologies.
Single stage telescopic amplifiers (Fig. 1 (i)) have good
bandwidth characteristics, are relatively simple in circuit
topology, and are not prone to phase margin problems.
However, when a large output swing is required, or when the
supply voltage is low, the gain of these amplifiers becomes
limited by the number of cascode transistors that can fit within
a given supply voltage.
Folded cascode amplifiers (Fig. 1 (ii)) provide a nice way to
get extra voltage swing out of a normal telescopic amplifier.
By folding the cascode node we can eliminate the extra
voltage headroom required for the tail current source, and we
can get a larger allowable input common mode voltage
movement. But these advantages come at a heavy price of 2x
increased power dissipation, larger noise (noise of current
sources at the folding nodes) and lower phase margin figures
(because of larger parasitic capacitance at the folding node).
Despite the disadvantages, these amplifiers are very popular at
low voltage supplies.
Regulated cascodes [3] (Fig. 1 (iii)) provide further means
of getting more gain with fewer number of cascode transistors,
and are thus very attractive for low supply voltages. But,
regulated cascodes need very controlled designs in order to
make them work. Without careful control one may end up
with a very unstable amplifier, or one with slow settling
behavior, even though the gain/phase plots indicate good
performance. We discuss regulated cascodes in more detail in
Section II and III.
Two-stage amplifiers [2] also have good gain and large
output swings, but they suffer from larger power
consumption, and they have to be compensated internally.
They are not output load compensated as are the topologies
we discussed above. Fig. 1 (iv) shows the topology of a
typical 2-stage amplifier which is compensated internally by a
miller capacitor.
The op-amp discussed in this paper is a folded cascode
amplifier with regulated cascodes for gain boosting. In
Section II we discuss the circuit topology and some circuit
analysis is given in Section II-B. Section III deals with the
frequency response of a regulated cascode amplifier. Section
IV gives the circuit implementation. Section V gives the
simulated results. Section VI addresses the layout, and we
conclude our discussion in section VII.
GROUP 8 FINAL PROJECT, FALL 2004, EECS 413, UNIVERSITY OF MICHIGAN, ANN ARBOR. 2

INP INM
VOUT VOUT

INP INM

(ii) Folded Cascode Amplifier

(i) Telescopic Amplifier

VREF
+ INP + - + -
- VOUT
INM
- + - +

(iv) 2-stage miller compensated Amplifier

(iii) Regulated Cascodes
Fig. 1. Typical Amplifier Topologies

II. CIRCUIT TOPOLOGY

A. Circuit Description cascode topology was used. The stringent requirement of a

In order to achieve a high DC gain of > 75dB at a supply phase margin of 65o (with feedback factor β = 1) led to a
voltage of 1.8V (2.0V ± 10%), we chose a folded cascode PMOS input folded cascode topology. Since the non-dominant
topology. The maximum gain that can be achieved with such a pole is at the folding node, choosing PMOS inputs greatly
topology in 0.25µm process is about 50dB. To meet the reduces the parasitic capacitance at this node.
additional 25dB of gain, regulated cascodes were
implemented for gain boosting. Fig. 2 shows the resulting
circuit topology.
B. Circuit Analysis + -
From the bandwidth requirement of 1GHz: - +
INM
Unity Gain Bandwidth (UGB) ~ gm/(CL+CP)
INP
For a CL of 1pF and CP of approximately the same value we
get as the following required gm: VOUT
gm ~ 12.6 mS
gm ~ 2.ID/(VGS - VTH)
For a nominal VGS - VTH of 200mV + -
ID ~ 1.3mA - +
The final current required to meet the bandwidth was
1.6mA.
With minimum supply voltage of 1.8V and output swing
requirement of 600mV pk-pk, we are left with 1.5V to fit in as
many number of transistors as possible. With a nominal VDSat
of 200mV and an additional 100mV margin, the maximum Fig 2. Implemented Circuit Topology
number of transistors is five. A single stage telescopic
topology was ruled out because of input common mode
voltage movement specifications. Thus, a single folded
GROUP 8 FINAL PROJECT, FALL 2004, EECS 413, UNIVERSITY OF MICHIGAN, ANN ARBOR. 3

IV. CIRCUIT IMPLEMENTATION

The nominal gain obtainable out of a single transistor in this Fig. 4 (i) shows the circuit implementation of the main
process is about 25dB. The single folded cascode stage gave amplifier. Fig. 4 (ii) shows the circuit implementation of the
us a DC gain of ~ 52dB and a phase margin of 65o. auxiliary amplifiers with simple CMFB loop. Fig. 4 (iii)
For the additional gain of ~ 25dB, regulated cascodes. with shows the CMFB used for the main amplifier.
fully differential auxiliary amplifiers (for both PMOS and
NMOS cascodes) were used.
Implementing the auxiliary amplifiers is a difficult job.
Considering the N-side auxiliary amplifiers, the input voltage
to these amplifiers is too low to be implemented using NMOS
inputs, while if we use PMOS inputs the output voltage
required is moderately high which pushes these input PMOS
transistors into linear region. We used a two-stage topology
where the first stage is a simple PMOS source follower, which
shifts the input voltage higher, and the second stage is a
simple differential amplifier with NMOS inputs. The other
challenge of implementing an auxiliary amplifier is setting the
bandwidth of the auxiliary amplifier. This is discussed in more
detail in Section III.
Fig 4 (i) Main Amplifier
III. REGULATED CASCODE FREQUENCY RESPONSE
Several papers have been published that deal with stability
of a regulated cascode amplifier [4][5][6]. It is a well known
fact that a low bandwidth auxiliary amplifier leads to a pole-
zero doublet causes a slow settling component in the transient
response of the amplifier in feedback mode. If the bandwidth
is too large, the amplifier may become unstable.
Figure 3 shows the bode plots of the amplifier with
regulated cascodes and the auxiliary amplifier. ωp1, ωp2 are
the dominant and non dominant poles of the amplifier, ωug is
the unity gain bandwidth of the amplifier. ωpx is the unity
gain bandwidth of the auxiliary amplifier.
Our main amplifier is basically a 2-pole system with a
phase margin of 65o. This implies that
ωp2 ~ 2.ωug
To avoid the pole-zero doublet, we need ωpx ≥ β.ωug, Fig 4 (ii) Auxiliary Amplifier
while for stability reasons ωpx < ωp2.
Because the gap between ωug and ωp2 is small in our main
amplifier, ωpx needs to be around ωug, as the amplifier will
typically be used with a feedback factor of β < 1, thus
avoiding the slow settling component.

Open Loop Gain

gain (dB)

Aux Amp

Closed Loop gain

1/β Safe range for

ωp1 βωug ωpx ωug ωp2 Fig 4 (iii) CMFB for Main Amplifier

log (ω)
Fig. 3. Safe range for the unity-gain frequency of auxiliary amplifier
GROUP 8 FINAL PROJECT, FALL 2004, EECS 413, UNIVERSITY OF MICHIGAN, ANN ARBOR. 4

V. SIMULATED RESULTS
Figure 5 shows the gain and phase response of the open-
loop amplifier both with and without the auxiliary amplifiers
at input common-mode voltages of 350mV and 650mV. The
main amp achieved a gain of about 50dB without the auxiliary
amplifiers, which provided about 25dB of additional gain.
This circuit is relatively insensitive to input common-mode
variation between 350mV and 650mV.
Fig. 7. Closed-loop frequency response with feedback factor of 1 and 0.5

Fig. 5. Bode plot of simulated amplifier. The solid line is the response of the Fig. 8. Closed-loop step response with feedback factor of 1 and 0.5
complete amplifier and the dashed line is the amplifier without gain boosting.
Note that each is simulated with common mode input voltages of 350mV and
650mV. A marker has been placed at the unity gain frequency.

Our initial design included compensation capacitors at the

output of the amplifier (100fF). The layout contributed
approximately 80fF of parasitic capacitance to each output
line. Thus, the compensation capacitors were no longer
needed. All results described were obtained following post-
layout parasitic extraction, with the exception of the aux amp
gain and the amplifier gain without aux amps.
Fig. 9. Closed-loop transient outputs for different feedback factors.
The unity gain bandwidth of the auxiliary amplifiers was
about 1GHz (see Fig. 6). These amplifiers provided about
25dB of gain.
Figure 7 shows the closed-loop response of the amplifier Table 1 summarizes our post-layout simulation results. Our
for β = 1 and β = .5, and the transient step responses for worst-case bandwidth occurred at Vdd = 1.8, T = 85C and our
worst-case phase margin of 63.25 o occurred at Vdd = 2.0V, T
= 85C. Additionally, the allowable input common-mode
variation was greater than 300mV and the output differential
swing was greater than 650mVp-p. This design consumes about
16.5mW of power when operating from a 2V supply

TABLE I: POST-LAYOUT SIMULATION RESULTS

Vdd Temp DC gain Phase Unity gain
(C) (dB) Margin BW (GHz)
1.8 27 78.77 63.68 1.14
1.8 85 76.35 63.52 1.02
Fig. 6. Gain of auxiliary amplifier. A marker is at the unity-gain frequency 2.0 27 79.17 63.56 1.15
2.0 85 79.61 63.25 1.03
2.2 27 79.21 63.32 1.16
feedback factors of 1 and .5 are shown in Fig. 8. The 2.2 85 77.01 62.92 1.05
response settles within 10 ns after the step input is applied.
Figure 9 shows transient closed-loop outputs for sine-wave
inputs. Note that the output differential swing is
approximately 650mVp-p.
GROUP 8 FINAL PROJECT, FALL 2004, EECS 413, UNIVERSITY OF MICHIGAN, ANN ARBOR.
VI. LAYOUT
The layout of this amplifier is shown in Fig. 10. The layout
is symmetrical for the main amplifiers and auxiliary
amplifiers. This layout was DRC and LVS clean, and
extracted parasitics were used for simulation results.
Fig. 10. Amplifier layout.
VII. CONCLUSION
An operational amplifier with a single stage folded cascode
topology and auxiliary amplifiers for gain boosting has been
presented. The amplifier is designed to operate from a 1.8 V
supply. To avoid instability and slow settling behavior in
closed loop feedback (β=1), the unity gain frequency of the
auxiliary amplifiers is carefully chosen to be close to the unity
gain frequency of the main amplifier. Following layout and
parasitic extraction, simulations show a low frequency gain of
around 79 dB, a phase margin of around 63o, and a unity gain
frequency of around 1 GHz across variation in temperature
and supply (see Table 1), when a 1 pF load is presented at the
output. The design allows for common mode input voltage
variation between 350 mV to 650 mV. Common mode
feedback is successfully employed to control the common
mode output voltage. The maximum output differential swing
is approximately 650mVp-p. The amplifier consumes around
16.8 mW of DC power.
APPENDIX
Our simulation file is stored in the following folder:
/afs/engin.umich.edu/class/f04/eecs413/group8
Our key cadence schematic:
final_Project/final (Library/Cell)
ACKNOWLEDGMENT
The authors would like to thank Professor Michael Flynn
and Matt Stamplis for their helpful support throughout the
project.
REFERENCES
[1] K. Shimohigashi and K. Seki, “Low-voltage VLSI design,” IEEE J.
Solid-State Circuits, vol. 28, no. 4, pp. 408-413, April 1993.
[2] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,”
Edition 2001, McGraw-Hill.
5
[3] Eduard Sackinger and Walter Guggenbuhl, “ A High-Swing, High
Impedance MOS Cascode Circuit,” IEEE J. Solid-State Circuits, vol.
25, no. 1, pp. 289-297, Feb. 1990.
[4] Klaas Bult and Govert J.G.M. Gleen, “A Fast-Settling CMOS Op Amp
for SC Circuits with 90-dB DC Gain,” IEEE J. Solid-State Circuits, vol.
25, no. 6, pp. 1379-1384, Dec. 1990.
[5] Kush Gulati and Hae-Seung Lee, “A High-Swing CMOS Telescopic
Operational Amplifier,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp.
2010-2019, Dec. 1998.
[6] Mrinal Das and Jim Hellums, “Improved Design Criteria of Gain-
Bossted CMOS OTA with High Speed Optimizations,” IEEE
International Symposium on Circuits and Systems, May 2000.
Chun C. Lee was born in Chandigarh, India, in 1980.
He received the B. Tech. degree in Electronics and
Communication Engineering from IIT Roorkee,
Roorkee, India, in 2002. He worked as a senior design
engineer in Texas Instruments, Bangalore, India, from
2002-2004. He is currently pursuing his M.S. (leading
to Ph.D.) degree at the University of Michigan, Ann
Arbor.
Jason W. May was born in Santa Clara, CA in 1983.
He received his B.S.E. in electrical engineering in 2004
from the University of Michigan in Ann Arbor,
Michigan. He is currently employed at Q-DOT, Inc. in
Colorado Springs, CO as an electrical engineer. His
research interests include implementing microwave
circuits in IC’s.
Alex Grichener was born in Chissinau, Moldova, in
1981. He received his B.S. in electrical engineering in
2003 from Tufts University in Boston, MA. He worked
as a lead software engineer/instrumentation engineer at
the National Radio Astronomy Observatory,
Charlottesville, VA, from 2003-2004. He is currently
pursuing his M.S. degree at the University of Michigan,
Ann Arbor. His research interests include RF MEMS and RFIC.