CMOS Digital Design II

Day 1

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TYPES

OF

IC DESIGNS
Designer Tasks Define Overall Chip A rchitect C/RTL Model Initial Floorplan Behavioral Simulation Logic Designer Logic Simulation Synthesis Datapath Schematics Cell Libraries Circuit Designer Circuit Schematics Circuit Simulation Megacell Blocks Layout and Floorplan Physical Designer Place and Route Parasitics Extraction DRC/LVS/ERC Place/Route Tools Physical Design and Evaluation Tools Schematic Editor Circuit Simulator Router RTL Simulator Synthesis Tools Timing A nalyzer Power Estimator Tools Text Editor C Compiler

Analog Digital

Full Custom Standard-cell based (ASIC)

from RTL

Semi-custom Steps in a design process

rony.ec@adishankara.ac.in

TYPES

OF

LOGIC STRUCTURES

Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: ??
clk in CL out CL CL clk clk clk

Finite State Machine

Pipeline

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WHY SEQUENTIAL DESIGN?

If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high 4 rony.ec@adishankara.ac.in Delay fast tokens so they dont catch slow

SEQUENCING OVERHEAD

Use registering elements to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence

rony.ec@adishankara.ac.in

RULES

FOR

RIGHT SEQUENCING

To Ensure Proper Sequencing of Data through a Sequential Circuit:

Rule 1: Data launched by a Flip-Flop SHOULD BE captured by the subsequent FF at the subsequent edge Rule 2: Data launched by a FF SHOULD NOT BE captured by the subsequent FF at the same edge
D F1 CLK D3
6

Example: A serial-in-serial-out shift register

D3D2D1D0

D F2

D F3

D F4

D2

D1

D0

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(IM)PROPER SEQUENCING
CLK Input D0 x D0 xxxx xxxx xxxx D1 D1 D0 D2 D2 D1 D0 D3 D3 D2 D1 D0

F1/Q F2/Q F3/Q F4/Q

What if:

7

F2 violates setup requirement? F2 violates hold requirement?

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STATIC TIMING ANALYSIS

Analyzing timing performance Flip-Flops and latches break signal flow by means of clock

Analogous to closing and opening valves in fluid pipe

Goal : every timing path to meet the required timing constraints Design divided into pairs of registers separated by combinational logic

Launch (start or source) register Capture (end or destination) register Many paths possible, each one starting at different start points Known as fanin cone rony.ec@adishankara.ac.in

For every endpoint register:

TIMING PATHS
F1 Path1 F(End as well as Start for next stage)

F2

Path2

Fn Path n

. .
in1 in 2 .

Fanin cone

rony.ec@adishankara.ac.in