Electrical engineering department

SESSION: JUNE/ DECEMBER 2020

DEC50143 – CMOS INTEGRATED CIRCUIT DESIGN AND FABRICATION

PRACTICAL WORK ASSESSMENT

TITLE INTRODUCTION TO L-EDIT SOFTWARE

PRACTICAL NUMBER 1/2/3/4/5/6
CLASS DTK5A

Item \ Student S1 S2 S3 S4 Scale Score

1. Technology Feature X2.5

2. Setting Computer X2.5

Practical Skill 3 Identify The Parts/ Polygons Correctly X5

Assessment
[CLO2 P4 4. Function of LEDIT X5
PLO5] 5. Exercise X5

6. Save file as. tdb X5

Total Practical Skill Assessment /70

X5
1. Appearance and Formatting
X5
Report 2. Documentation
Assessment X5
3. Conclusion

Total Report Assessment /30

REGISTER TOTAL
STUDENTS NAME NUMBER MARKS/100
S1 NURUL NABILA BINTI ANUAR 10DTK18F1025
S2 NUR ALYA MAISARAH BINTI RIDWAN 10DTK18F1042

LECTURER’S NAME PUAN LIM BEE LING DATE 21/8/2020

Objectives:

1. Able To Use L-Edit Software.

2. Draw an CMOS Inverter Layout by using L-Edit

Laboratory Equipment:

1. Lab sheet

2. L-Edit Software

3. P-Spice

Procedures:

1. Launch L-Edit

Before launch L-Edit, make sure it running in the 256 colors condition. If not, right click the
icon and click on ‘Properties’, then select ‘ Run in the 256 colors’ in the ‘Compatibility’ tab.
Start L-Edit. Ignore all pop-up warnings (click Yes). This is shown in Figure 1 below:

Figure 1: L-Edit Main Screen

2. Procedures:

1. Using L-Edit software, draw layout for inverter CMOS (Figure 4). Name vdd, vss, input
and output ports. All ports must in one dimension only.

2. Make sure the layout are free from error by doing DRC (Design Rules Check)

3. Name the layout (cell) with inverter. Click Cell -> Rename -> Inverter

4. Name the file that saves the cell as inverter.tdb. Click File -> Save

5. Do cross section by click Tools -> Cross Section

6. Get spc file by extract the layout. Click Tools -> Extract

7. Simulate your layout using SPICE.

Figure 2: Layout of Inverter CMOS

Steps:

3. Draw the layout:

a. PMOS

i. N-well

ii. P-select

iii. Active

iv. Poly

b. NMOS

i. Do not need to draw P-Well because the empty grid of L-Edit stands for P-Well.

ii. N-select

iii. Active

iv. Poly

c. Metal VDD & GND

d. Connect to VDD & GND

i. PMOS

1. Place a small N-Select on N-well

2. Add small active layer

3. source PMOS connect to VDD (Metal)

4. Active Contact

ii. NMOS

1. Place a small P-Select

2. Add a small active layer

3. Source NMOS connect to VSS (Metal)

4. Active Contact

e. Connection

i. Poly PMOS -> Poly NMOS -> (input) Place small metal to poly
ii. Drain PMOS -> drain NMOS -> (output) Place small metal

iii. Active Contact

iv. Poly contact

f. Port name: Input, Output, Vss and Vdd

i. Make sure select correct layer when you put port name

4. Run DRC

i. Run DRC for the total layout.

ii. Tool DRC

iii. If got error, find error layer: Edit find.

Figure 3: Design Rule Check

5. Cross Section

i. Tool cross section

ii.. Browse mamin12.xst

iii. Pick the center of the gate (rotate to suitable/horizontal)

Figure 4: Cross Section

6. Extract

i. Tool -> extract

ii. General tab: Browse mamin12.ext as definition file. Browse/name a SPC file name.

Figure 5: Extract (general)

iii. Output tab: check all comments and nodal parasitic capacitance as figure 8 below

Figure 6: Extract (output)

iv. Click Run.

v. Click Ignore all the warning.

vi. Open .spc file in notepad. Make sure got node names and netlist is correct.
 Figure 7: Netlist

vii. Copy the netlist as highlight in yellow color(figure 9).

viii. Simulation
a. Open template.cir given by lecturer

b. Copy the netlist from .spc file and paste into template.cir

c. Save the template.cir

d. Open MicroSim Eval 8 -> Pspice_AD

e. File -> Open template.cir -> click OK if simulation completed successfully

f. File -> Run Probe

g. Add Plot

h. Click on a plot: Trace Add -> v(input)

i. Click on another plot: Trace Add -> v(output)

j. Check the output

Exercise:

1. Show the simulation graph base on the cmos inverter layout result.

2. Build the truth table base on the simulation of the cmos inverter layout result.

Vin T1 T2 Vout
0 Off On 1
1 Off Off 0
 3. Draw the schematic diagram and stick diagram for the cmos inverter.

Schematic diagram and stick diagram

Conclusion:

Write the conclusion of the practical work.

For conclusion, we’re able to use L-Edit software and draw an CMOS inverter layout
by using L-Edit then name vdd, vss, input and output ports. For drawing the layout, we have
to draw PMOS and NMOS part using N-well, P-well, N-select, P-select, Active, Poly and
Metal1. After that, we have to make sure the layout are free from error by doing DRC
(Design Rules Check). We also learn how to tool cross section and extract. Lastly, we learn
how to simulation layout using Pspice to get Vin and Vout.