BY-

VISHAL PATYAL
3050060122
An Introduction
Talk Flow:
Introduction.
Concept of clock.
Working of synchronous circuits.
Problem of synchronous circuits.
Concept of clockless chip.
Working of asynchronous circuit.
Advantages of clockless design.
Applications.
Challenges.
Conclusion.
References.

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 Concept of clock
CLOCK:
Tiny crystal oscillator.

Sets basic rhythm used throughout the machine.

ADVANTAGES:

 Signals the device of the chip when to i/p or o/p.

This functionality makes designing of synchronous chip easier.

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Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
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continued…
This circuit looks for a particular signal(leading edge) of
the clock.

All actions takes place only at this part of clock cycle.

When transferring data to registers the computation

settles down and wait till the next leading edge

Designer’ challenge: to complete one operation before

next clock tick.

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Problems of synchronous
circuit
Speed
 chip can only work as fast as its slowest component.
 leads to wasting of computation time.
 to traverse the chip’s longest wire in one clock cycle.
 so one alternate solution: Second clock incur

overhead and power consumption.

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continued…
Power consumption
Consume more power than any other component.

Not associated with direct computation.

If no. of transistors more power consumption more.

EMI(Electro Magnetic Interference)

It is more in synchronous elements.

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Concept of Clockless
chip
Clockless chip/asynchronous/self timed/event driven.

Do not have a global clock.

Rely upon handshaking signals , hand-off signals and

sometimes a local clock to synchronize all actions.

Draw power only when there is useful work to do.

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Continued…
Chip can run at the average speed of all
components.

Different part work at different speeds.

Hand-off the result immediately.

Very low Electro Magnetic Noise.

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Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
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Continued…
TYPES OF
IMPLEMENTATION:
BOUNDED DELAY METHOD
similar to synchronous design

DELAY INSENSITIVE METHOD

opposite of bounded delay method

NULL CONVENTIONAL LOGIC(NCL)

it uses a NULL state when data is in reset
phase,
as opposed to data in set phase.
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Continued…
BOUNDED DELAY METHOD:
Simplest implementation of asynchronous
design.

Assumption: we know the largest amount of

time for each component to perform its task.

Very similar to synchronous design.

Prototype delay is introduced here.

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Continued…
DELAY INSENSITIVE METHOD:
Does not assume
any bound on time.

One method of this

type is : Dual-rail
method.

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Continued…
NULL CONVENTIONAL LOGIC:
NCL integrates data transformation and
control into a single expression.

It gives solutions for power , noise and system

integration issue.

NCL uses threshold gates with hysteresis.

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Advantages of clockless design:
Increase in speed

Reduced power consumption

Less Electro Magnetic Noise

Flexible design

Provide superior encryption

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Applications:
In the lab.

In mobile electronics.

In personal computers.

In encryption devices.

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 19
Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
Challenges
Design difficulties.

Lack of good tools.

Engineers are not trained in these fields.

Academically, no courses available.

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Conclusion:
Clocks are getting faster , while chips are
getting bigger, both of which make clock
distribution harder. There are also various
other problems associated with it. So we could
only get out of it , if more focus , especially at
the university level is given to the
asynchronous design. It is certainly a challenge
, but as software community is moving
towards concurrency, hardware community
must move to incorporate asynchronous logic.

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References:
 David Geer , “ Is it time for clock less chips?
 http://www.google.com
 http://www.howstuffworks.com
 http://www.guruji.com

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QUERIES??

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