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Demux to ALU

Demux to ALU

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Published by karry4gals

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Published by: karry4gals on Dec 23, 2009
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08/30/2012

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Exp. No. 6 (a) : 1x2 DEMULTIPLEXER in GATE LEVEL
Code
`timescale 1ns / 1psmodule Demux1x2_GL(Out0,Out1,S,In);output Out0,Out1;input S,In;not (Sbar,S);and (Out0,Sbar,In);and (Out1,S,In);endmodule 
Test bench
`timescale 1ns / 1psmodule tb_Demux1x2_GL;reg S,In;wire Out0,Out1;// Instantiate the Unit Under Test (UUT)Demux1x2_GL uut (Out0,Out1,S,In);initialbeginS = 0;In = 0;#40 S=1;#40 $finish;endalways #2 In=~In; endmodule
 
Exp. No. 6 (b) : 1x2 DEMULTIPLEXER in DATAFLOW
Code
`timescale 1ns / 1psmodule Demux1x2_DF(Out0,Out1,S,In);output Out0,Out1;input S,In;assign Out0=(~S)&In;assign Out1=S&In;endmodule 
Test bench
`timescale 1ns / 1psmodule tb_Demux1x2_DF;reg S,In;wire Out0,Out1;// Instantiate the Unit Under Test (UUT)Demux1x2_DF uut (Out0,Out1,S,In);initialbeginS = 0;In = 0;#40 S=1;#40 $finish;endalways
 
 #2 In=~In; endmodule 
Exp. No. 6 (c) : 1x2 DEMULTIPLEXER using CONDITIONAL OPERATOR
Code
`timescale 1ns / 1psmodule Demux1x2_CondOper(Out0,Out1,S,In);output Out0,Out1;input S,In;assign Out0=S? 0 : In;assign Out1=S? In : 0;endmodule 
Test bench
`timescale 1ns / 1psmodule tb_Demux1x2_ CondOper;reg S,In;wire Out0,Out1;// Instantiate the Unit Under Test (UUT)Demux1x2_ CondOper uut (Out0,Out1,S,In);initialbegin

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