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2 Lesson
Embedded Processors and
6
Memory Memory-II
Version 2 EE IIT, Kharagpur 1 Version 2 EE IIT, Kharagpur 2
Instructional Objectives 6.2 Cache
After going through this lesson the student would x Usually designed with SRAM
faster but more expensive than DRAM
Memory Hierarchy x Usually on same chip as processor
Cache Memory space limited, so much smaller than off-chip main memory
- Different types of Cache Mappings faster access (1 cycle vs. several cycles for main memory)
- Cache Impact on System Performance x Cache operation
Dynamic Memory Request for main memory access (read or write)
- Different types of Dynamic RAMs First, check cache for copy
Memory Management Unit cache hit
- copy is in cache, quick access
Pre-Requisite cache miss
- copy not in cache, read address and possibly its neighbors into cache
Digital Electronics, Microprocessors x Several cache design choices
cache mapping, replacement policies, and write techniques
6.1 Memory Hierarchy
6.3 Cache Mapping
Objective is to use inexpensive, fast memory
x Main memory x is necessary as there are far fewer number of available cache addresses than the memory
Large, inexpensive, slow memory stores entire program and data x Are address’ contents in cache?
x Cache x Cache mapping used to assign main memory address to cache address and determine hit
Small, expensive, fast memory stores copy of likely accessed parts of larger memory or miss
Can be multiple levels of cache x Three basic techniques:
Direct mapping
Fully associative mapping
Process Set-associative mapping
x Caches partitioned into indivisible blocks or lines of adjacent memory addresses
usually 4 or 8 addresses per line
Registers
Direct Mapping
Cache
x Main memory address divided into 2 fields
Index which contains
Main memory - cache address
- number of bits determined by cache size
Tag
Disk - compared with tag stored in cache at address indicated by index
- if tags match, check valid bit
Tape x Valid bit
indicates whether data in slot has been loaded from memory
x Offset
Fig. 6.1 The memory Hierarchy used to find particular word in cache line
V T D V T D
V T D Data
Valid
Data
= =
Valid
=
0.16 In
Sense
Buffer
Addr Amplifiers
0.14 Data Col Decoder ras, clock
rd/ wr Col cas
0.12
% cache miss
Row
0.1 1 way Out Buff Decod cas,
Buffer er
2 way er
0.08 Data Addr.
4 ways
Row ras
0.06 8 way address Bit storage array
0.04
Fig. 6.6 The Basic Dynamic RAM Structure
0.02
6.12 Question
Q1. Discuss different types of cache mappings.
Q2 Discuss the size of the cache memory on the system performance. ras
cas
Ans:
address row col
0.16
data data data data
0.14
0.12
0.1 1 way
% cache miss
2 way
0.08
4 ways
0.06 8 way
0.04
0.02
0
cache size
1 Kb 2 Kb 4 Kb 8 Kb 16 Kb 32 Kb 64 Kb 128 Kb
Ans:
EDO RAM
ras
cas