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3. Cache Memories
• Secondary memory: slow, cheap, direct access,
4. Cache Organization located remotely from the CPU.
5. Replacement Algorithms
6. Write Strategies
7. Virtual Memory
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What do we need?
We need memory to fit very large programs and to It is possible to build a composite memory system
work at a speed comparable to that of the which combines a small, fast memory and a large
microprocessors. slow main memory and which behaves (most of the
time) like a large fast memory.
Main problem:
- microprocessors are working at a very high rate The two level principle above can be extended into a
and they need large memories; hierarchy of many levels including the secondary
memory (disk store).
- memories are much slower than microproces-
sors;
increasing capacity
1. Processor registers:
Register
5. Hard disk:
- capacity = few Gbytes
- access time = tens of milliseconds
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• The data which is held in the registers is under the processor memory
direct control of the compiler or of the assembler
programmer. registers
instructions
• The contents of the other levels of the hierarchy are
managed automatically:
- migration of data/instructions to and from address instructions
caches is performed under hardware control; and data
- migration between main memory and backup
copies of address
store is controlled by the operating system (with data
hardware support). instructions
copies
of data
instructions
cache and data
• The miss rate of a well-designed cache: few % Temporal locality (locality in time): If an item is
referenced, it will tend to be referenced again soon.
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Problems concerning cache memories: • The figure on slide 8 shows an architecture with a
unified instruction and data cache.
• It is common also to split the cache into one dedi-
cated to instructions and one dedicated to data.
• How many caches?
instruction memory
• How to determine at a read if we have a miss or hit? cache
address
• If there is a miss and there is no place for a new slot copies of
in the cache which information should be replaced? instructions
instructions
instructions
• How to preserve consistency between cache and
main memory at write? address instructions
processor
registers
address
copies
of data
data
data cache
Cache Organization
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Direct Mapping
Direct Mapping (cont’d)
8bit 14bit 2bit
Set 0
Disadvantage:
cmp
if miss
This can produce a low hit ratio, even if only a very if hit
small part of the cache is effectively used. miss hit
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• A memory block is mapped into any of the lines of a • Set associative mapping keeps most of the
set. The set is determined by the memory address, advantages of direct mapping:
but the line inside the set can be any one. - short tag field
- fast access
• If a block has to be placed in the cache the - relatively simple
particular line of the set will be determined
according to a replacement algorithm.
• Set associative mapping tries to eliminate the main
shortcoming of direct mapping; a certain flexibility is
• The memory address is interpreted as three fields given concerning the line to be replaced when a
by the cache logic, similar to direct mapping. new block is read into the cache.
However, a smaller number of bits (13 in our
example) are used to identify the set of lines in the
cache; correspondingly, the tag field will be larger • Cache hardware is more complex for set
(9 bits in our example). associative mapping than for direct mapping.
• The number of lines in a set is determined by the • if a set consists of a single line ⇒ direct mapping;
designer;
2 lines/set: two-way set associative mapping If there is one single set consisting of all lines ⇒
4 lines/set: four-way set associative mapping associative mapping.
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Replacement Algorithms
Associative Mapping (cont’d)
• First-in-first-out (FIFO):
The candidate line is selected which holds
the block that has been in the cache the
longest.
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Write Strategies
Write Strategies (cont’d)
• Copy-back
Write operations update only the cache memory
• Write-through which is not kept coherent with main memory;
All write operations are passed to main memory; if cache lines have to remember if they have been
the addressed location is currently hold in the updated; if such a line is replaced from the cache,
cache, the cache is updated so that it is coherent its content has to be copied back to memory.
with the main memory.
PowerPC 603
- two on-chip caches, for data and instructions
- each cache: 8 Kbytes
- line size: 32 bytes
- 2-way set associative organization
(simpler cache organization than the 601 but
stronger processor)
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virtual address
Only one part of the program fits into main memory; the MMU
rest is stored on secondary memory (hard disk).
physical address
• In order to be executed or data to be accessed, a
Cache
certain segment of the program has to be first
loaded into main memory; in this case it has to data/instructions physical address
replace another segment already in memory.
Main memory
• Movement of programs and data, between main
memory and secondary storage, is performed
transfer if
automatically by the operating system. These
reference not in
techniques are called virtual-memory techniques.
physical memory
pages
Demand Paging
• The program consists of a large amount of pages
which are stored on disk; at any one time, only a
few pages have to be stored in main memory.
• The operating system is responsible for loading/ frames in main
replacing pages so that the number of page faults is memory
minimized. pages on the disk
• We have a page fault when the CPU refers to a
location in a page which is not in main memory; this
page has then to be loaded and, if there is no
available frame, it has to replace a page which
previously was in memory.
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If page fault
then OS is
Total number of pages: 220 = 1M activated in
Total number of frames: 213 = 8K order to load
missed page
Problems:
- The page table is very large (number of pages
• The page table has one entry for each page of the in virtual memory space is very large).
virtual memory space. - Access to the page table has to be very fast ⇒
the page table has to be stored in very fast
• Each entry of the page table holds the address of memory, on chip.
the memory frame which stores the respective
page, if that page is in main memory.
• Each entry of the page table also includes some • A special cache is used for page table entries,
control bits which describe the status of the page: called translation lookaside buffer (TLB); it works in
- whether the page is actually loaded into main the same way as an ordinary memory cache and
memory or not; contains those page table entries which have been
- if since the last loading the page has been most recently used.
modified; • The page table is often too large to be stored in
- information concerning the frequency of main memory. Virtual memory techniques are used
access, etc. to store the page table itself ⇒ only part of the
page table is stored in main memory at a given
moment.
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Page in
No main
(page fault) memory?
OS activated:
- loads missed Yes
page into main update TLB
memory;
- if memory is generate physical
full, replaces address
an "old" page;
- updates page access cache
table and, if miss,
main memory