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Co-Processors
The modeling of reconfiguration overhead is divided into two steps. In the first step,
different technology-dependent features are mapped onto a set of parameters, which
are the size of configuration data, the clock speed of configuration and the extra
delays apart from loading of the configuration data. In the second step, a SystemC
module that models the behavior of run-time reconfiguration process is created and is
used in system-level simulation to reveal the reconfiguration overhead.
A general SystemC model of RSoC is shown in Fig. 1. The left side is an overview
of the RSoC. The DRC is a single SystemC module, which implements the same bus
interfaces in the same way as other HW/SW modules. A configuration memory is
modeled, which could be an on-chip or off-chip memory that holds the configuration
data. The right side shows the internal structure of the DRC, which is in fact a
hierarchical SystemC module. Each candidate component (F1 to Fn) is an individual
SystemC module, which implements the top-level bus interfaces with separate system
address space, and is instantiated inside the DRC. Each candidate component has two
extra ports. One is a DONE signal port routed to the Configuration Scheduler (CS).
The port is used to acknowledge the CS that this task can be safely swapped out. The
other is connected to a shared memory that saves the data to be preserved during
reconfiguration. The Input Splitter (IS) is an address decoder and it manages all
incoming Interface-Method-Calls (IMCs). The CS monitors the operation states of the
candidate components and controls the reconfiguration process.
3 Case Study
A MPEG2 decoder case is chosen to prove the approach is very useful for the task of
fast design space exploration. The starting point is a SystemC transaction-level model
of a static architecture of the decoding system. Control-oriented tasks, such as
variable-length decoding, are assigned to a RISC processor. Motion compensation is
assigned to a DSP core. The color converter (CC), which processes 8 pixels in
parallel, and the IDCT are assigned to two separate hardwired ASICs. A shared
memory and a one-level system bus are used. The task is to study the possibility of
moving the IDCT and the CC from ASIC implementation to a DRC.
The DRC is a Virtex2-like FPGA. The partial, single/multi-context reconfiguration
are to be considered. Features of the target DRC are as following. There are 3200
LUTs and 40 multipliers available. The size of bitstream to configure the full device
is 200k bytes. In partial reconfiguration, the size of configuration data is proportional
to the number of LUTs required. In the multi-context reconfiguration, there are two
layers of programming bits and 5 clock cycles are required for context switching. The
configuration clock is running at 50MHz, and 8 bits are loaded every cycle.
We started with the estimation of the requirement of the configuration data in
partial reconfiguration. The estimation tool showed 2983 LUTs and 2688 LUTs were
required for the IDCT and the CC separately, which correspond to 186k and 168k
configuration data. Three simulation packages were created using the modeling
method described in section 2.2 and the simulation results are given in Table 1. The
differences between three configuration styles are clearly revealed. Designers can
easily make design decisions when information of ASIC area of the two functions and
the estimates of design time are available.
The case study proves the approach is useful in helping designers to rapidly
perform design space exploration. The estimation tool can produce results within
minutes without any manual effort. In the SystemC modeling, the transformation tool
can significantly reduce the amount of coding work. Designers need to edit only the
script file of the design parameters, which can be easily done within a minute.
4 Conclusions
References
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SystemC. Proc. IPDPS’03 (2003) 174-181
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