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1. Introduction
4. Conclusion
1. Introduction
2. Device layout consideration
A. Device type
a. Trans
b. Resister
c. Capacitor
d. BJT
e. OP Amplifier
f. SCF
g. ADC/DAC
B. Process variation
3 By Johnson Liu / NOVATEK
Workshop on Fully Layout Technology 2002 / 03 / 23
Mask 在曝光時,多多少少都會產生
繞射的問題。尤其是在最外圍的 Polygon
因光折射的角度較大,所以容易改變
Width 和 Length。中間部份則因為每一
個 Polygon寬度及間距都相同,所以繞射
的結果都差不多。
M1 M2 M1 M2 M1 M2
S D S D S D S D S D S D
M1 M2
M1 M2
D S D
S D S D
M2 M1
M2 M1
S D S D D S D
WRONG
Idd Idd
Idd Idd
RIGHT
Wrong
( W- ? W
L- ? L
) ( W- ? W
L- ? L
)X2 ( W- ? W
L- ? L
) X4
7 Right By Johnson Liu / NOVATEK
Workshop on Fully Layout Technology 2002 / 03 / 23
op
sp3 sp30
2 2
p3 p30
2 2 p2a
P1 p2 p1a n1 n2 n 1a n 2a
n2 n1 n 2a n 1a
2 2 n3 n3 n 30 n 30
2 2
n1 n2 n1a n2a
sn 3 sn 30
sp 3 sp 30
p3 p3 p 30 p30
2
n3 2 n30 p2 p1 p 2a p 1a
p1 p2 p1a p 2a
sn30
sn3
8 8 8 8 BIAS
P19 P19 P21 P21 P23 P23 P27 P27 P19 P19 P21 P21 P23 P23 P27 P27
P27 P27 P23 P23 P21 P21 P19 P19 P27 P27 P23 P23 P21 P21 P19 P19
P20 P20 P22 P22 P24 P24 P28 P28 P20 P20 P22 P22 P24 P24 P28 P28
P28 P28 P24 P24 P22 P22 P20 P20 P28 P28 P24 P24 P22 P22 P20 P20
3 2 2 4 8 16 DAC
A B C D E F
DAC Switch
V V V V V V
DUMMY
DUMMY
DUMMY
DUMMY
C A C F F F F F F F F C B C C C D D E E E E F C
C C C C C C
Better
V V V V V V V
DUMMY
DUMMY
DUMMY
DUMMY
C A C C E E E E D D C C A C B C F F F F F F F C
C C C C C C C
Practice
OUT
M3 M4 M6 M6 M3 M4 M6 M6
M1 M2
M1 M2
C
C M2 M1
M8
M2 M1 M8
M5 M5 M7 M7
M5 M5 M7 M7
I 2I 4I 8I
→ current cell
→ transistor matching
M1 M2 M3 M4
M4 M4 M4 M4 M3 M3 M2 M1 M2 M3 M3 M4 M4 M4 M4
Common centroid
b. Resistor
Resistor type L
* poly
* well
* diffusion ( N+ , P+ ) W
1. poly W
R=2 Rcont + ( ) R/•
L
Double poly
{ poly gate
poly resistor → sheet resistor 較大 , 特性較佳 ( voltage cofe. )
Sheet 最 大
Spacing 大
→ 面積最小 ?
3. diffusion P-SUB
N+ , ( if P-sub ) → noisy
P-SUB guard ring P+
P+ , in N-well → better
if no double poly process
→ Diffusion is better
N-well
2K
2K
Better
2K
450 650 90
0
2
K
Worse
450 650 900
2K 2K 2K 1K 2
K
用 2K 並聯 2K → 1K
2K
2K
2K → 浪費面積
19 By Johnson Liu / NOVATEK
Workshop on Fully Layout Technology 2002 / 03 / 23
1K
1K 2K 1K
A B
A B
2K
C D
用 1K 串 聯 1K = 2K
A 1K B
A 1K 2K 1K B
C 2K D
Worse
C A D
A 1K B
A 1K 1K 1K 1K B
1K 1K 1K
C 1K 1K D
Good
C D
A B A
DUMMY
DUMMY
DUMMY
DUMMY
1K
1K
1K
1K
1K 1K 1K
B
Better
B C
D
A 4K 2K 1K
B C
3 2 3 1 3 2 3
DUMMY
DUMMY
4K 4K 4K 4K 4K 4K 4K
B D
Resistor grading
R6
V5
R5
V4
R4
V3
R3 R1 R2 R3 R4 R5 R6
V2
R2
V1
R1
V5
V4
V3
V2
V1
R1>R2>R3>R4>R5>R6
R3 100(100)
200 200
R2 100(90)
180 180
R1 100(80)
160 160
110
105
100
95 160 X 240
90 160 // 240 = =96
160 + 240
180 X 220
96 180 // 220 = =99
180 + 220
99
100
R3 R2 R1 R2 R3
99
96
c. Capacitor A
C type C =
A
, A < 100 x 100 µ²
- d
* Mos B
* Double poly
* Mmc
* Sandwich
MOS A Poly A Poly
B B
P+ N+ N+ P+ N+ P+ P+ N+
N well
P SUB P SUB
Double poly
A
Poly 2
A
N well
ONO 200? 300 Å
B Poly 1
B Poly 2
Poly 1
N+ N+
N well
P SUB
25 By Johnson Liu / NOVATEK
Workshop on Fully Layout Technology 2002 / 03 / 23
MMC
1.5 KÅ
B M4
Field oxide
N+ N+
N well
P SUB
M4 MMC M5
B A
Sandwich
A
M4
10 KÅ +
M3
M3 M3 M1 M1
B M2 A
M4 M2 M2 POLY
M1
poly
Field oxide -
B
N+ N+
N well
P SUB
N well
A
B
Poly & M2 & M4 M1 & M3
29 By Johnson Liu / NOVATEK
Workshop on Fully Layout Technology 2002 / 03 / 23
→ Cap. array
-
+
16C 8C 4C 2C 1C
C5 C4 C3 C2 C1
P
P
C4 C4 C4
C3 C3 C4 C4
C2 C3 C4 C4
C1 C2 C3 C4
32 By Johnson Liu / NOVATEK
Workshop on Fully Layout Technology 2002 / 03 / 23
C4 C4 C4
C4 C3 C3
C3 C3 C4
C4 C4 C4
Poly
contact
較差
dummy
*PNP
B NPN
B PNP
C C
C E B
C E B
P+ N+ P+ N+ P+ P+ N+ P+
N+ N+
N-well P-well
P-SUB N-SUB
N+
P+
P+
N-well C B E C B E
N+
NPN 10 NPN 10
E = 10 X 10 X 1 E = 10 X 10 X 8
Q1 Q2
E = 10 X 10 X 1 E = 10 X 10 X 8
E = 10 X 10 X 2
Q5
Q3 Q4 NPN 10
NPN 10
NPN 10
Q2 Q2 Q2 Q4 Q4 Q4 Q5
Q2 Q1 Q2 Q4 Q3 Q4 Q5 dummy bjt
Q2 Q2 Q2 Q4 Q4 Q4 QD
a.Input stage MOS (PIP&IN; NIP&IN)需 要 個 別 以 common-centroid 方式 layout, 以降低 offset voltage.
b. 對 稱 之MOS( 1_33 & 1_31 ; 1_30 & T_28 ; PL3 & PL4 ; NB1 & NB2 ), 亦需 layout 成同一方向互相對稱。
g. ADC/DAC
DAC LAYOUT 注意事項 :
1. DAC LAYOUT
49226 49226 49226 49226 49226 49226 49226 49226 49226 49226
R
R
RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7 RN8 RN9
A
A
0
9
5
24697
24697
24697
24697
24697
24697
24697
24697
24697
24697
2. LAYOUT ( 附圖一 )
3. 說 明 :
3-1:DAC 擺設以先決定電阻之 LAYOUT 方式,再 LAYOUT 其 他 DEVICE,因電阻所用之 LAYER
不同,相對值也不同,而影響 PLAN AND BLOCK SIZE?
3-4:DAC之輸出點接至鄰近線路之輸人端必須愈短愈好,最好.其週圍用GND LINE 將
其圈住,以隔離其他信號,防止電容效應產生 NOISE 干 擾 ?
附圖一
Output
-
TOP Layer +
1C 1C 2C 4C 8C 16C 32C 64C 128C
Bottom Layer
2 : 說明 :
2 –1:ADC 中 CAPACITOR ARRAY 宜盡量排成近似正方形佈局然後將 1C、2C 、4C 、 8C 、 16C 、 64C、 128C
電容拆成兩半左右對稱佈局主要 在避免 PROCESS 變化而影響電容比值 ?
OP-Amp
c -
+
Analog ground
f. SCF
POLY Ⅰ
POLY Ⅱ 信號線
METAL
GND
CONTACT
3: 若有 ANALOG BLOCK AND DIGITAL BLOCK 同置於 CHIP 中彼此 BLOCK 須用分開且
每一 BLOCK 必須各自獨立一條 POWER LINE 如此可避免NOISE COUPLE ?
4 : ANALOG BLOCK 四週必須用 VCC OR GND RING 圍住,以防止 DIGITAL BLOCK
NOISE COUPLE,此 VCC OR GND LINE 為獨立之 POWER LINE 且不接任何 DEVICE?
5: ANALOG 內各小 BLOCK 之 POWER 必須從 POWERPAD 處分開獨立連接,此 POWER LINE 不 允 許
挖 SUBSTRATE OR WELL CONTACT,以 防 止 BLOCK 間 NOISE 經由 SUBSTRATE INJECTION?
PAD PAD
OUT BUFF OUT BUFF
ROM ANALOG
RAM RAM
CPU ROM
PAD
PAD
PAD
PAD
DIGITAL DIGITAL
CPU
ANALOG
PAD PAD
Metal 1 Metal 2
Metal 1
poly poly
Metal 2
Shielding layer
Metal 1 Metal 1
poly poly
GND
Line 1
GND
Analog Line
GND
Digital Line
*well isolation
C. Coupling from power line
POWER
POWER POWER
PAD
PAD DIGITAL DIGITAL DIGITAL
PAD
a c e
POWER
POWER
PAD
POWER DIGITAL PAD DIGITAL DIGITAL
POWER
PAD PAD
PAD ANALOG
ANALOG PAD ANALOG
POWER
POWER
b d f
55 By Johnson Liu / NOVATEK