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Description
CXA2074Q CXA2074S
The CXA2074Q/S is an IC designed as a decoder
48 pin QFP (Plastic) 42 pin SDIP (Plastic)
for the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in while
adjustment, mode control and sound processor
control are all executed through I2C BUS.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96843B86
CXA2074Q/S
CXA2074Q
VCAWGT
VEWGT
AUX1-R
AUX1-L
VEOUT
VCATC
VCAIN
SAPIN
VETC
NC
NC
VE
36 35 34 33 32 31 30 29 28 27 26 25
AUX2-R 37 24 SAPOUT
AUX2-L 38 23 NOISETC
LPOUT-R 39 22 STIN
LPOUT-L 40 21 SUBOUT
LPIN-R 41 20 NC
LPIN-L 42 19 VCC
NC 43 18 SAPTC
BASSR1 44 17 GND
BASSR2 45 16 IREF
BASSL1 46 15 VGR
BASSL2 47 14 COMPIN
TRER 48 13 PLINT
1 2 3 4 5 6 7 8 9 10 11 12
SDA
NC
NC
LSOUT-R
SCL
MAININ
PCINT1
LSOUT-L
DGND
MAINOUT
PCINT2
TREL
CXA2074S
LPOUT-R
NOISETC
VCAWGT
SUBOUT
LPOUT-L
SAPOUT
VEWGT
AUX1-R
AUX2-R
AUX1-L
AUX2-L
VCATC
VEOUT
LPIN-R
LPIN-L
VCAIN
SAPIN
VETC
STIN
VCC
VE
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
LSOUT-L
DGND
BASSR2
LSOUT-R
SDA
TRER
BASSL1
PCINT2
MAINOUT
TREL
PCINT1
MAININ
BASSL2
COMPIN
PLINT
SAPTC
SCL
VGR
BASSR1
IREF
GND
–2–
Block Diagram
CXA2074Q
AUX1-R
MAINOUT
PCINT1
MAININ
PCINT2
PLINT
SUBOUT
AUX1-L
11 12 13 21 9 8 36 35
STLPF
"FILTER"
FEXT1
LFLT VCO 1/4 1/2
38 AUX2-L
MATRIX TVSW
37 AUX2-R
FLT LPF VCA
FEXT2
40 LPOUT-L
"STEREO" WIDEBAND
COMPIN 14 VCA LPF DeEm LPF 39 LPOUT-R
NRSW/FOMO/SAPC
TVSW/EXT/M1
(+6dB) 42 LPIN-L
ATT PASSSW
STIND
PSW
41 LPIN-R
VCC 19
LOGIC
GND 17
–3–
VOL-L
SAPVCO
VOL-L
BPF LPF
VOL-R
VOL-R
46 BASSL1
DeEm VE VCA
NOISETC 23 NOISE 47 BASSL2
DET "NOISE"
HPF 44 BASSR1
RMSDET
"SAP"
BASS
BASS
BASS
SW
M2 TREBLE
"PONRES"
15 16 6 5 4 24 25 22 26 27 28 30 31 33 32 3 2
VE
SCL
SDA
VGR
IREF
STIN
VETC
SAPIN
VCAIN
DGND
VCATC
VEOUT
VEWGT
SAPOUT
LSOUT-L
VCAWGT
LSOUT-R
CXA2074Q/S
CXA2074S
AUX1-L
AUX1-R
MAINOUT
PCINT1
MAININ
PCINT2
PLINT
SUBOUT
14 15 16 23 13 12 36 35
STLPF
"FILTER"
FEXT1
LFLT VCO 1/4 1/2
38 AUX2-L
MATRIX TVSW
37 AUX2-R
FLT LPF VCA
FEXT2
40 LPOUT-L
"STEREO" WIDEBAND
COMPIN 17 VCA LPF DeEm LPF 39 LPOUT-R
TVSW/EXT/M1
NRSW/FOMO/SAPC
(+6dB) 42 LPIN-L
PASSSW
PSW
GND 20
–4–
VOL-L
VOL-L
VOL-R
SAPVCO
VOL-R
BPF LPF
3 BASSL1
DeEm VE VCA
NOISETC 25 NOISE 4 BASSL2
DET "NOISE"
1 BASSR1
HPF RMSDET
"SAP"
BASS
BASS
BASS
SW
M2 TREBLE
"PONRES"
18 19 11 10 9 26 27 24 28 29 30 31 32 34 33 8 7
VE
SCL
SDA
VGR
IREF
STIN
VETC
DGND
SAPIN
VCAIN
VCATC
VEOUT
VEWGT
LSOUT-R
SAPOUT
LSOUT-L
VCAWGT
CXA2074Q/S
CXA2074Q/S
Pin Description
VCC
3k
2.7k
2.2k
1.8k
1.4k
VCC
TREBLE filter pin.
1.2k
1 6 TREL (Left channel)
4.0V 4.9k (Connect a 6.8nF capacitor
(48) 5
between this pin and GND.)
(1) 6
VCC
3k
LSOUT right channel output
2 7 LSOUT-R 4.0V VCC pin.
580
(2) 7
(3) 8 580
–5–
CXA2074Q/S
VCC
7.5k
↓ 35µ
2.1V
4k
×2
Serial data I/O pin.
4 9 SDA — ×5 VIH > 0V
4.5k 3k
7.5k VIL < 1.5V
9
(4)
VCC
7.5k
↓ 35µ
2.1V
4k Serial clock input pin.
×4
VIH > 3.0V
5 10 SCL — 10.5k 3k VIL < 1.5V
10
(5)
11
6 11 DGND — Digital block GND.
(6)
VCC
10k
4V
VCC
15k
×4
VCC
↓ 1k
200µ
–6–
CXA2074Q/S
VCC
147
14
(11) 30k
11 14 PCINT1 4.0V
22k
147
15
(12) 10k 10k
12 15 PCINT2 4.0V
2k
×2
4k
VCC
20k 20k
↓ 20k ↓ 10k
26µ 50µ
VCC
50k 147
17
(14)
Audio multiplexing signal
14 17 COMPIN 4.0V 22k 20k
3k input pin.
3V
4k 4k 4k 16k 24k
–7–
CXA2074Q/S
VCC
40k 40k 30k 30k 15k 30k
×2
Set the filter and VCO
reference current. The
reference current is adjusted
VCC
with the BUS DATA based
16 19 IREF 1.3V on the current which flows to
30p 1.8k this pin.
19 (Connect a 62kΩ (±1%)
147 (16) resistor between this pin and
GND.)
6.3k
16k
20
17 20 GND — Analog block GND.
(17)
VCC
8k
10k
3k 1k
Set the time constant for the
VCC SAP carrier detection circuit.
18 21 SAPTC 4.5V 4k (Connect a 4.7µF capacitor
↓ 50µ between this pin and GND.)
21
(18)
–8–
CXA2074Q/S
Vcc
2k 2k
10P
4k
580
21 23 SUBOUT 4.0V 23 (L – R) signal output pin.
14.4k 580 147
2k 2k (21)
2k 4k 1k
VCC
23k 23k Input the (L – R) signal from
22 24 STIN 4.0V
SUBOUT (Pin 23 (21)).
11.7k
147 147
24 27
SAPIN (22) 18k 18k (25) Input the (SAP) signal from
25 27 4.0V
SAPOUT (Pin 26 (24)).
4V 20k 4V
Vcc
8k 3.3k
10k
1k
Set the time constant for the
2k
4k noise detection circuit.
23 25 NOISETC 3.0V ×2 (Connect a 4.7µF capacitor
4V between this pin and GND.)
3k Vcc 3k
200k
25
(23)
Vcc
5P
580
SAPOUT 4.0V
580 10k SAP FM detector output pin.
24 26
26
147 (24)
24k 4k
↓ 10µ ↓ 50µ
–9–
CXA2074Q/S
VCC
7.5k
Variable de-emphasis
147 integrating pin.
26 28 VE 4.0V 28 (Connect a 2700pF capacitor
(26) and a 3.3kΩ resistor in series
between this pin and GND.)
Vcc
Vcc
Determine the restoration
time constant of the variable
de-emphasis control
effective value detection
30
×4 ×4 circuit.
28 30 VETC 1.7V (28)
(The specified restoration
time constant can be
20k obtained by connecting a
4k ↓ 7.5µ 3.3µF capacitor between this
↓ 50µ pin and GND.)
Vcc
5P
Variable de-emphasis output
580
pin.
30 31 VEOUT 4.0V 31 (Connect a 4.7µF non-polar
(30) 10k capacitor between Pins 31
580
(30) and 32 (31).)
– 10 –
CXA2074Q/S
VCC
47k 47k
VCA input pin.
20k Input the variable
31 32 VCAIN 4.0V VCC de-emphasis output signal
from Pin 31 (30) via a
32
coupling capacitor.
(31)
VCC
Determine the restoration
time constant of the VCA
×4 33 control effective value
×4
(32) detection circuit.
32 33 VCATC 1.7V (The specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
4k 20k
↓ ↓ pin and GND.)
50µ 7.5µ
VCC
40k 40k 3p
– 11 –
CXA2074Q/S
VCC
3k
LPOUT right channel output
39 39 LPOUT-R 4.0V
pin.
147 580
39
580
40
LPOUT left channel output
40 40 LPOUT-L 4.0V
pin.
VCC
41 41 LPIN-R 4.0V Right channel loop input pin.
10k
147
41
42
47k
42 42 LPIN-L 4.0V Left channel loop input pin.
4V
7 — NC — (7)
10 — NC — (10)
20 — NC — (20)
29 — NC — (29)
34 — NC — (34)
43 — NC — (43)
– 12 –
Electrical Characteristics Main (L + R) (Pre-Emphasis: OFF) = 245mVrms
COMPIN input level SUB (L – R) (dbx-TV: OFF) = 490mVrms
(100% modulation level) Pilot = 49mVrms
The pin numbers in parenthesis are for the CXA2074Q.
SAP Carrier = 147mVrms
fH = 15.734kHz (Ta = 25°C, VCC = 9V)
Measurement Output
No. Item Signal Mode Input pin Input signal Filter Min. Typ. Max. Unit
conditions pin
– 13 –
(14) Pre-em. ON ('100%'/'0%')
17 SUB (L-R), 1kHz, 23
8 Sub output level Vsub ST 150 190 230 mVrms
(14) 100% mod., NR OFF (21)
Sub LPF frequency 17 SUB (L-R) 12kHz, 20 log 23
9 FCsub ST –3.0 –0.5 1.0 dB
characteristic (14) 30% mod., NR OFF ('12k'/'1k') (21)
17 SUB (L-R) 1kHz, 23
10 Sub distortion THDsub ST 15kLPF – 0.1 1.0 %
(14) 100% mod., NR OFF (21)
17 SUB (L-R), 1kHz, 23
11 Sub overload distortion THDsmax ST 15kLPF – 0.2 2.0 %
(14) 200% mod., NR OFF (21)
17 SUB (L-R) 1kHz, 20 log 23
12 Sub S/N SNsub ST 15kLPF 56 64 – dB
(14) NR OFF ('100%'/'0%') (21)
SUB (L-R), 1kHz, 20 log
ST → SAP 17 1kBPF
13 CTst SAP 100% mod., NR ON, ('NRSW = 0'/ 40 60 70 – dB
Crosstalk (14) SAP Carrier (5fH) 'NRSW = 1')
14 Sub pilot leak 17 PILOT (fH) 0dB 0dB = 49mVrms fH BPF 23 –27 dB
PCsub ST – –35
(14) (21)
– 14 –
(14) NR ON
17 ST-R 3kHz 30% mod.
27 ST separation 2 R → L STRsep2 ST 15kLPF 39/40 23 35 – dB
(14) NR ON
28 35/36 Sine wave 1kHz,
LPOUT output level Vtp EXT 0dB = 490mVrms 39/40 –0.5 0 0.5 dB
37/38 490mVrms
– 15 –
37/38 245mVrms 0dB = 245mVrms (2/3)
SDA
SCL
– 16 –
CXA2074Q/S
CXA2074Q
S6
S5
S4
BUFF
S3
FILTERS MEASURES
SIGNAL SIGNAL SIGNAL SIGNAL S2
GENE- GENE- GENE- GENE- S1 15kHz LPF
RATOR RATOR RATOR RATOR
fH BPF
V2 V4 V5 V6 1kHz BPF
AC AC AC AC
TANTALUM
TANTALUM
R1 C15 R4 R6
3.9k 4.7µ 3k 3.3k
C10 C12 C13 C14 C17 C18 C19
4.7µ 4.7µ 1µ 10µ 3.3µ 0.047µ 2700p
36 35 34 33 32 31 30 29 28 27 26 25
C28
VETC
VCAIN
NC
VE
NC
VCATC
AUX1-R
VEWGT
VEOUT
VCAWGT
AUX1-L
SAPIN
4.7µ
C2
37 24
4.7µ SAPOUT
AUX2-R
38 AUX2-L NOISETC 23
C3
C22
4.7µ
4.7µ
39 LPOUT-R STIN 22
C4
4.7µ
C29
40 LPOUT-L SUBOUT 21
C5 4.7µ
SIGNAL
4.7µ
GENERATOR
41 LPIN-R NC 20
C6
4.7µ
V1
AC
42 LPIN-L VCC 19
C7 C23 VCC
V3
4.7µ 100µ
AC V8
43 NC SAPTC 18 9V
SIGNAL C24 GND
GENERATOR 4.7µ
44 BASSR1 GND 17
GND
C8 R8
45 BASSR2 IREF 16
47n 62k METAL ± 1%
46 BASSL1 VGR 15
C25 SIGNAL
10µ GENERATOR
C9
47n
47 BASSL2 COMPIN 14
C26 V7
MAINOUT
LSOUT-R
4.7µ AC
LSOUT-L
PCINT1
PCINT2
MAININ
48 TRER PLINT 13
DGND
GND
TREL
C27
SDA
SCL
C1
NC
NC
6.8n 1µ
1 2 3 4 5 6 7 8 9 10 11 12
R7
C11 R2 R3 C20 1MEG
6.8n 220 220 C16 5600P
4.7µ
R5 C21
I2C BUS DATA 100k 0.012µ
DGND
– 17 –
CXA2074S
S
6
S
5
S
4 BUFF
S
3 FILTER MEASURE
S S S
SIGNAL SIGNAL SIGNAL SIGNAL
GENERATOR GENERATOR SIGNAL
2
GENERATOR GENERATOR S
GENERATOR 15kHz LPF
SIGNAL 1
V1 V2 V3 V4 V5 V6 fH BPF
GENERATOR
1kHz BPF
AC AC AC AC AC AC
R2 R5 R7
C1 C3 C4 C6 C8 C10 C12 C14 3.9k 3k 3.3k C28 C31
4.7µ 4.7µ 4.7µ 4.7µ 4.7µ 4.7µ 4.7µ 4.7µ C17 C25 4.7µ C29 100µ
C15 4.7µ C21 C23
C16 10µ
4.7µ 4.7µ
C19 3.3µ
1µ 0.047µ 2700p
TANTALUM
TANTALUM
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VE
VCC
VCC
STIN
V8
VETC
VCAIN
SAPIN
LPIN-L
LPIN-R
VCATC
VEOUT
AUX1-L
AUX2-L
AUX1-R
AUX2-R
9V
VEWGT
SAPOUT
LPOUT-L
SUBOUT
VCAWGT
LPOUT-R
NOISETC
– 18 –
GND
MAININ
DGND
SCL
SDA
LSOUT-L
LSOUT-R
BASSL2
BASSL1
BASSR2
BASSR1
TREL
TRER
SAPTC
GND
IREF
VGR
COMPIN
PLINT
PCINT2
PCINT1
MAINOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
R6
1MEG
C24 C26 C27 C30
C7 C9 C11 C13 R1 R3 C20 5600p 1µ 4.7µ 10µ
C2 C5 C18 4.7µ
R8 62k
R4 C22
100k 0.012µ
SIGNAL
GENERATO
R GND
V7
I2C BUS DATA
AC
GND
DGND
CXA2074Q/S
CXA2074Q/S
SPECTRAL 6 A 1F
WIDEBAND 6 A 1F
TEST-DA 1 T 0
Normal mode Standard setting value
TEST1 1 T 0
FST 1 T 0 Normal mode FST = 0
VOL-L 6 U 3F 3F = 0dB
VOL-R 6 U 3F 3F = 0dB
BASS 4 U 8 7 or 8 = 0dB
TREBLE 4 U 8 7 or 8 = 0dB
NRSW 1 U —
According to the mode control table
FOMO 1 U —
TVSW 1 U 0
TV decoder output selection Standard setting value
EXT 1 U 0
FEXT1 1 U 0 External input 1 forced MONO Standard setting value
FEXT2 1 U 0 External input 2 forced MONO Standard setting value
PSW 1 U 0 TVSW output selection Standard setting value
M1 1 U 1
Mute OFF
M2 1 U 1
ATTSW 1 S —
Fixed by the set specifications
SAPC 1 S —
Classification A: Adjustment
U: User control
S: Proper to set
T: Test
– 19 –
List of Adjustment Contents The pin numbers in parenthesis are for the CXA2074Q.
– 20 –
CXA2074Q/S
CXA2074Q/S
Adjustment Method (Adjust this IC through Tuner and IF when this IC is mounted on the set.)
1. ATT adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LPOUT-L output level. Then,
adjust the “ATT” data for ATT adjustment so that the LPOUT-L output goes to the standard value
(490mVrms).
3) Adjustment range: ±30%
Adjustment bits: 4 bits
Adjustment point
Control data
"FILTER"
0 3F
1
Measurement data
0 STA5 "FILADJ"
4.Separation adjustment
1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz
NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce LPOUT-R output to
the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to
reduce LPOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
5) “WIDEBAND” “SPECTRAL”
Adjustment range: ±30% Adjustment range: ±15%
Adjustment bits: 6 bits Adjustment bits: 6 bits
– 21 –
CXA2074Q/S
Description of Operation [The pin numbers in parenthesis are for the CXA2074Q.]
The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz AM-DSB-SC
50 50
L-R
dbx-TV
25 25 NR
PILOT
15
SAP
dbx-TV NR TELEMETRY
L+R 5 FM 10kHz FM 3kHz
50 – 15kHz 50 – 10kHz 3
I2C BUS
2fHL0° DECODER
PLL PILOT
fHL90° MODE
(VCO 8fH) DET
fHL0° CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
– 22 –
CXA2074Q/S
38 37 42 41
(LPOUT-L) (LPOUT-R)
40 39 (LSOUT-L)
(AUX1-L) BASS TREBLE
VOL-L
36 8 (3)
TVSW PASSSW
35 7 (2)
VOL-R
(AUX1-R) (LSOUT-R)
(Lch) (Rch)
from MATRIX
(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 17 (Pin 14)) passes through MVCA, the
SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are
canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency
characteristics are flattened (de-emphasized) and input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 26 output is
soft muted.
– 23 –
CXA2074Q/S
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.
(8) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 19 (Pin 16)) with GND become the reference current.
Input pin Pin No. Input level LPOUT output level LSOUT output level∗3
17
COMPIN 245mVrms∗1 490mVrms∗2 490mVrms∗2
(14)
AUX1-L/AUX1-R 36/35 490mVrms 490mVrms 490mVrms
AUX2-L/AUX2-R 38/37 490mVrms 490mVrms 490mVrms
LPIN-L/LPIN-R 42/41 490mVrms — 490mVrms
∗1 MONO, 25kHz Deviation, Pre-Em. off
∗2 MONO, 25kHz Deviation, Pre-Em. on
∗3 VOLUME MAX, BASS & TREBLE CENTER
– 24 –
CXA2074Q/S
Register Specifications
Slave address
Register table
Status Registers
when TEST1 = 0
when TEST1 = 1
– 25 –
CXA2074Q/S
Description of Registers
Control registers
– 26 –
CXA2074Q/S
Status registers
ATT (4): Adjust the signal level input to COMPIN (Pin 17 (Pin 14)) to the standard input level (245mVrms).
Variable range of the input signal: 245mVrms –5.0dB to +3.0dB
0 = Level min.
F = Level max.
VCO (6): Adjust STEREO & SAP VCO free running frequency (fo).
Variable range: fo ±20%
0 = Free running frequency min.
3F = Free running frequency max.
FILTER (6): Adjust the filter fo of the ST, SAP and dbx blocks.
Variable range: fo ±20%
0 = Frequency min.
3F= Frequency max.
TEST-DA (1): Set DAC output test mode and VCO adjustment mode.
0 = Normal mode
1 = DAC output test mode and VCO adjustment mode
In addition, the following outputs are present at Pins 40 and 39.
LPOUT-L (Pin 40): DA control DC level
LPOUT-R (Pin 39): STEREO VCO oscillation frequency (4fH)
– 27 –
CXA2074Q/S
TVSW (1): Select TV mode or external input mode for LPOUT output.
0 = TV mode
1 = External input mode
EXT (1): Select external input [1] mode or external input [2] mode for LPOUT output. (TVSW = 1)
0 = External input [1] mode
1 = External input [2] mode
– 28 –
CXA2074Q/S
PSW (1) Select INT mode or LPIN mode for LSOUT output.
0 = INT mode
1 = LPIN mode
– 29 –
CXA2074Q/S
“Select dbx input and TV decoder output” “Select dbx input and TV decoder output”
Conditions: FOMO = 0 Conditions: FOMO = 0
NRSW = 0 (MONO or ST output) NRSW = 0 (MONO or ST output)
• During ST input: left channel: L, As on the left
right channel: R
• During other input: left channel: L + R,
NRSW right channel: L + R
NRSW = 1 (SAP output) NRSW = 1 (SAP output)
• When there is “SAP” during SAP • Regardless of the presence of SAP
discrimination discrimination,
– left channel: SAP, right channel: SAP dbx input: “SAP”
• When there is “No SAP”, output is the left channel: SAP, right channel: SAP
same as when NRSW = 0. However, when there is no SAP, SAPOUT
output is soft muted (–7dB)
“Forced MONO”
FOMO FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC = 0: Switch to SAP output when there is SAP discrimination.
SAPC
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.
“MUTE”
M1/M2 M1 = 0: LPOUT output is muted.
M2 = 0: LSOUT output is muted.
“TEST1”
TEST1 = 1
Return adjustment data with STATUS REGISTER as an adjustment mode.
TEST1
In addition, outputs are as follows.
left channel: SAP BPF OUT
right channel: NR BPF OUT
“TEST-DA”
TEST-DA = 1
TEST-DA Used to adjust the D/A TEST and VCO.
left channel: D/A output
right channel: STVCO oscillation frequency (4fH)
– 30 –
CXA2074Q/S
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 31 –
CXA2074Q/S
Note
(SAP) : The SAPOUT output signal is soft muted (approximately –7dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is
inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 32 –
CXA2074Q/S
H L HIZ L
• I2C transfer begins with Start Condition and ends with Stop Condition.
SDA
SCL
– 33 –
CXA2074Q/S
L during Write
MSB MSB LSB
HIZ HIZ
SDA
SCL 1 2 3 4 5 6 7 8 9 1 8 9
S
Address ACK Sub Address ACK
MSB LSB
HIZ HIZ
1 8 9 1 8 9
HIZ HIZ
H during Read
HIZ
SDA
SCL 1 6 7 8 9 1 7 8 9
S P
Address ACK DATA ACK
• Read timing
MSB LSB
IC output SDA
SCL 9 1 2 3 4 5 6 7 8 9
Read timing
ACK DATA ACK
– 34 –
CXA2074Q/S
Input level vs. Distortion characteristics 1 (MONO) Input level vs. Distortion characteristics 2 (Stereo)
Distortion [%]
0.1 1.0
–10 0 10
Input level [dB]
1.0
– 35 –
CXA2074Q/S
Gain [dB] 0
–5
–10
0 20 40 60 80 100
Frequency [kHz]
30
20
Gain (FC main and FC sub) [dB]
10
–10
–20
–30
–40
–50
1 2 5 7 10 20 50 70 100
Frequency [kHz]
20 90
5fH
80
Gain
10 70
Group delay [µs]
60
Gain [dB]
0 50
40
–10 30
20
Group delay
–20 3.8fH 10
6.2fH
0
20 40 60 80 100 120
Frequency [kHz]
– 36 –
CXA2074Q/S
BASS-TREBLE characteristics
+8
Boost amount [dB]
+4
–4
–8
–12
Input: AUX1, 2
245mVrms
Output: LSOUT
Volume characteristics
–20
LSOUT output level [dB]
–40
–60
–80
Input: AUX1, 2
1kHz, 490mVrms
Output: LSOUT
–100
0 F 1F 2F 3F
Control data VOL-L, VOL-R
– 37 –
CXA2074Q/S
15.3 ± 0.4
+ 0.4 + 0.1
12.0 – 0.1 0.15 – 0.05
36 25
0.15
37 24
13.5
48 13 + 0.2
0.1 – 0.1
1 12
0.9 ± 0.2
+ 0.15
0.8 0.3 – 0.1
± 0.12 M
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
CXA2074S
42PIN SDIP (PLASTIC) 600mil
– 0.05
+ 0.1
+ 0.4
37.8 – 0.1
0.25
42 22
15.24 ± 0.25
+ 0.3
13.0 – 0.1
0° to 15°
1 21
1.778 ± 0.25
+ 0.4
4.6 – 0.1
0.5 MIN
3.0 MIN
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
– 38 –