Aaa|oe 0|a|oeae 30-00, Septemher (2005) 1

A Pract|ca| 0a|de to |eh-Speed

Pr|ated-0|rca|t-8oard la)oat
Bv 1chn ^rdlzzcnl |jchn.ardlzzcnlanalce.ocm]
Despie is criical naure in high-speed circuiry, prined-circui-
board (PCB) layou is ofen one of he las seps in he design
process. There are many aspecs o high-speed PCB layou;
volumes have been wrien on he subiec. This aricle addresses
high-speed layou from a pracical perspecive. A maior aim is o
help sensiize newcomers o he many and various consideraions
hey need o address when designing board layous for high-speed
circuiry. Bu i is also inended as a refresher o beneh hose
who have been away from board layou for a while. No every
opic can be covered in deail in he space available here, bu we
address ley areas ha can have he greaes payoff in improving
circui performance, reducing design ime, and minimizing ime-
consuming revisions.
Alhough he focus is on circuis involving high-speed op amps,
he opics and echniques discussed here are generally applicable
o layou of mos oher high-speed analog circuis. When op amps
operae a high RI frequencies, circui performance is heavily
dependen on he board layou. A high-performance circui design
ha lools good "on paper can render mediocre performance
when hampered by a careless or sloppy layou. Thinling ahead and
paying aenion o salien deails hroughou he layou process
will help ensure ha he circui performs as expeced.
Ihe Schemat|c
Alhough here is no guaranee, a good layou sars wih a good
schemaic. Be houghful and generous when drawing a schemaic,
and hinl abou signal ow hrough he circui. A schemaic ha
has a naural and seady ow from lef o righ will end o have a
good ow on he board as well. Pu as much useful informaion
on he schemaic as possible. The designers, echnicians, and
engineers who will worl on his iob will be mos appreciaive,
including us; a imes we are asled by cusomers o help wih a
circui because he designer is no longer here.
Wha lind of informaion belongs on a schemaic besides he
usual reference designaors, power dissipaions, and olerances?
Here are a few suggesions ha can urn an ordinary schemaic
ino a superschemaic! Add waveforms, mechanical informaion
abou he housing or enclosure, race lenghs, leep-ou areas;
designae which componens need o be on op of he board;
include uning informaion, componen value ranges, hermal
informaion, conrolled impedance lines, noes, brief circui
operaing descripions . (and he lis goes on).
Irast No 0ae
If you`re no doing your own layou, be sure o se aside ample
ime o go hrough he design wih he layou person. An ounce of
prevenion a his poin is worh more han a pound of cure! Don`
expec he layou person o be able o read your mind. Your inpus
and guidance are mos criical a he beginning of he layou process.
The more informaion you can provide, and he more involved you
are hroughou he layou process, he beer he board will urn
ou. Cive he designer inerim compleion poinsa which you
wan o be noihed of he layou progress for a quicl review. This
"loop closure prevens a layou from going oo far asray and will
minimize reworling he board layou.
Your insrucions for he designer should include: a brief descripion
of he circui`s funcions; a slech of he board ha shows he inpu
and oupu locaions; he board stac/ up (i.e., how hicl he board
will be, how many layers, deails of signal layers and planespower,
http:,,www.aaa|oe.com,aaa|oed|a|oeae
ground, analog, digial, and RI); which signals need o be on each
layer; where he criical componens need o be locaed; he exac
locaion of bypassing componens; which races are criical; which
lines need o be conrolled-impedance lines; which lines need o
have mached lenghs; componen sizes; which races need o lep
away from (or near) each oher; which ctrcutts need o be lep away
from (or near) each oher; which ccmpcnents need o be close o (or
away from) each oher; which componens go on he op and he
boom of he board. You`ll never ge a complain for giving someone
oo much informaionoo /ttt/e, yes; oo much, no.
/earntng expertence. Abou 1u years ago I designed a
mulilayer surface-mouned boardwih componens on
boh sides of he board. The board was screwed ino a gold-
plaed aluminum housing wih many screws (because of a
sringen vibraion spec). Bias feed-hrough pins poled up
hrough he board. The pins were wire-bonded o he PCB.
I was a complicaed assembly. Some of he componens on
he board were o be ST (se a es). Bu I hadn` specihed
where hese componens should be. Can you guess where
some of hem were placed? Righ! On he boom of he
board. The producion engineers and echnicians were no
very happy when hey had o ear he assembly apar, se
he values, and hen reassemble everyhing. I didn` male
ha misale again.
locat|oa, locat|oa, locat|oa
As in real esae, locaion is everyhing. Where a circui is placed
on a board, where he individual circui componens are locaed,
and wha oher circuis are in he neighborhood are all criical.
Typically, inpu-, oupu-, and power locaions are dehned, bu
wha goes on beween hem is "up for grabs. This is where paying
aenion o he layou deails will yield signihcan reurns. Sar
wih criical componen placemen, in erms of boh individual
circuis and he enire board. Specifying he criical componen
locaions and signal rouing pahs from he beginning helps ensure
ha he design will worl he way i`s inended o. Ceing i righ
he hrs ime lowers cos and sressand reduces cycle ime.
Power-Sapp|) 8)pass|ae
Bypassing he power supply a he ampliher`s supply erminals o
minimize noise is a criical aspec of he PCB design processboh
for high-speed op amps and any oher high-speed circuiry. There
are wo commonly used conhguraions for bypassing high-speed
op amps.
Rat/s tc grcund. This echnique, which worls bes in mos cases,
uses muliple parallel capaciors conneced from he op amp`s
power-supply pins direcly o ground. Typically, wo parallel
capaciors are sufhcienbu some circuis may beneh from
addiional capaciors in parallel.
Paralleling differen capacior values helps ensure ha he
power supply pins see a low ac impedance across a wide band of
frequencies. This is especially imporan a frequencies where he
op-amp pcver-supp/y reiecttcn (PSR) is rolling off. The capaciors
help compensae for he ampliher`s decreasing PSR. Mainaining
a low impedance pah o ground for many decades of frequency
will help ensure ha unwaned noise doesn` hnd is way ino he
op amp. Iigure 1 shows he benehs of muliple parallel capaciors.
A lower frequencies he larger capaciors offer a low impedance
pah o ground. Once hose capaciors reach self resonance, he
capaciive qualiy diminishes and he capaciors become inducive.
Tha is why i is imporan o use muliple capaciors: when one
capacior`s frequency response is rolling off, anoher is becoming
signihcan, hereby mainaining a low ac impedance over many
decades of frequency.
2 Aaa|oe 0|a|oeae 30-00, Septemher (2005)
1M
100k
10k
1k
100
10
1
0.1
0.01
0.001
0.001 10k 1k 100 10 1 0.1 0.01
FREQUENCY (MHz)
I
M
P
E
D
A
N
C
E

(
6
)
100pF
1000pF
0.01MF
0.1MF
2.2MF
Fleure 1. Capaoltcr lmpedanoe vs. frequenov.
Saring direcly a he op amp`s power-supply pins; he capacior
wih he lowes value and smalles physical size should be placed
on he same side of he board as he op ampand as close o he
ampliher as possible. The ground side of he capacior should
be conneced ino he ground plane wih minimal lead- or race
lengh. This ground connecion should be as close as possible o
he ampliher`s load o minimize disurbances beween he rails
and ground. Iigure 2 illusraes his echnique.
-V
S
+V
S
+
+
BYPASS
CAPACITORS
BYPASS
CAPACITORS
LOAD
Fleure 2. laralleloapaoltcr rallstcercund bvpasslne.
This process should be repeaed for he nex-higher-value
capacior. A good place o sar is wih u.u1 MI for he smalles
value, and a 2.2-MIor largerelecrolyic wih low ESR for he
nex capacior. The u.u1 MI in he u5uS case size offers low series
inducance and excellen high-frequency performance.
Rat/ tc rat/. An alernae conhguraion uses one or more bypass
capaciors ied beween he posiive- and negaive supply
rails of he op amp. This mehod is ypically used when i is
difhcul o ge all four capaciors in he circui. A drawbacl o
his approach is ha he capacior case size can become larger,
because he volage across he capacior is double ha of he
single-supply bypassing mehod. The higher volage requires a
higher brealdown raing, which ranslaes ino a larger case size.
This opion can, however, offer improvemens o boh PSR and
disorion performance.
Since each circui and layou is differen; he conhguraion,
number, and values of he capaciors are deermined by he acual
circui requiremens.
Paras|t|cs
Parasiics are hose nasy lile gremlins ha creep ino your PCB
(quie lierally) and wreal havoc wihin your circui. They are he
hidden sray capaciors and inducors ha inhlrae high-speed
circuis. They include inducors formed by paclage leads and
excess race lenghs; pad-o-ground, pad-o-power-plane, and
pad-o-race capaciors; ineracions wih vias, and many more
possibiliies. Iigure 3(a) is a ypical schemaic of a noninvering
op amp. If parasiic elemens were o be alen ino accoun,
however, he same circui would lool lile Iigure 3(b).
In high-speed circuis, i doesn` ale much o inuence circui
performance. Someimes ius a few enhs of a picofarad is
enough. Case in poin: if only 1 pI of addiional sray parasiic
capaciance is presen a he invering inpu, i can cause almos
2 dB of pealing in he frequency domain (Iigure 4). If enough
capaciance is presen, i can cause insabiliy and oscillaions.
R
G
V
I
A
V
= R
F
/R
G
+ 1
-V
+V R
F
R
L
(a)
TRACE
PAD
-V
+V
PAD
VIA
PAD
TRACE
PAD
TRACE
PAD
PAD
PAD PAD
V
O R
G
R
F
R
L
VIA
V
I
PAD
PAD
PAD
PAD
(b)
Fleure 3. Tvploal cp amp olroult. as deslened (a) and wlth parasltlos (b).
Aaa|oe 0|a|oeae 30-00, Septemher (2005) 3
10
8
6
4
2
0
1 300 100 30 10 3
FREQUENCY (MHz)
G
A
I
N

(
d
B
)
0pF
1pF
Fleure 4. ^ddltlcnal peaklne oaused bv parasltlo oapaoltanoe.
A few basic formulas for calculaing he size of hose gremlins
can come in handy when seeling he sources of he problemaic
parasiics. Equaion 1 is he formula for a parallel-plae capacior
(see Iigure 5).

C
/
d

11 3 .
pI

(1)
C is he capaciance, is he area of he plae in cm
2
, / is he
relaive dielecric consan of board maerial, and d is he disance
beween he plaes in cenimeers.
A
d
Fleure 5. Capaoltanoe between twc plates.
Srip inducance is anoher parasiic o be considered, resuling
from excessive race lengh and lacl of ground plane. Equaion 2
shows he formula for race inducance. See Iigure 6.

Inducance H
+ ( )
+
+ |
(
'
`
J
J
+

]
]
]
]
u uuu2
2
u 2235 u 5 . ln . . L
L
1 H
1 H
L


(2)
1 is he race widh, L is he race lengh, and H is he hiclness
of he race. All dimensions are in millimeers.
H
L
W
Fleure 6. lnduotanoe cf a traoe leneth.
The oscillaion in Iigure 7 shows he effec of a 2.54-cm race
lengh a he noninvering inpu of a high-speed op amp. The
equivalen sray inducance is 29 nH (nanohenry), enough o
cause a susained low-level oscillaion ha persiss hroughou he
period of he ransien response. The picure also shows how using
a ground plane miigaes he effecs of sray inducance.
2.88
2.00
1.00
0.57
211.9 220.0 230.0 240.0 250.0
TIME (ns)
V
O
L
T
A
G
E

(
V
)
Fleure 7. lulse respcnse wlthand wlthcutercund plane.
Vtas are anoher source of parasiics; hey can inroduce boh
inducance and capaciance. Equaion 3 is he formula for parasiic
inducance (see Iigure S).

L T
T
d
+

]
]
]
2
4
1 ln nH

(3)
T is he hiclness of he board and d is he diameer of he via
in cenimeers.
d
D
1
D
2
GROUND PLANE
d
D
1
D
2
T
Fleure 8. vla dlmenslcns.
Equaion 4 shows how o calculae he parasiic capaciance of
a via (see Iigure S).

C
TD
D D
r

u 55
1
2 1
. r
pI

(4)
d
r
is he relaive permeabiliy of he board maerial. T is he
hiclness of he board. D
1
is he diameer of he pad surrounding
he via. D
2
is he diameer of he clearance hole in he ground plane.
All dimensions are in cenimeers. A single via in a u.157-cm-hicl
board can add 1.2 nH of inducance and u.5 pI of capaciance;
his is why, when laying ou boards, a consan vigil mus be lep
o minimize he inhlraion of parasies!
4 Aaa|oe 0|a|oeae 30-00, Septemher (2005)
0roaad P|aae
There is much more o discuss han can be covered here, bu we`ll
highligh some of he ley feaures and encourage he reader o
pursue he subiec in greaer deail. A lis of references appears a
he end of his aricle.
A ground plane acs as a common reference volage, provides
shielding, enables hea dissipaion, and reduces sray inducance
(bu i also increases parasiic capaciance). While here are many
advanages o using a ground plane, care mus be alen when
implemening i, because here are limiaions o wha i can and
canno do.
Ideally, one layer of he PCB should be dedicaed o serve as he
ground plane. Bes resuls will occur when he enire plane is
unbrolen. Resis he empaion o remove areas of he ground
plane for rouing oher signals on his dedicaed layer. The ground
plane reduces race inducance by magneic-held cancellaion
beween he conducor and he ground plane. When areas of he
ground plane are removed, unexpeced parasiic inducance can
be inroduced ino he races above or below he ground plane.
Because ground planes ypically have large surface and cross-
secional areas, he resisance in he ground plane is lep o a
minimum. A low frequencies, curren will ale he pah of leas
resisance, bu a high frequencies curren follows he pah of
leas tmpedance.
Neverheless, here are excepions, and someimes less ground
plane is beer. High-speed cp amps will perform beer if he
ground plane is removed from under he inpu and oupu pads.
The sray capaciance inroduced by he ground plane a he inpu,
added o he op amp`s inpu capaciance, lowers he phase margin
and can cause insabiliy. As seen in he parasiics discussion, 1 pI
of capaciance a an op amp`s inpu can cause signihcan pealing.
Capaciive loading a he oupuincluding srayscreaes a pole
in he feedbacl loop. This can reduce phase margin and could
cause he circui o become unsable.
Analog and digial circuiry, including grounds and ground planes,
should be lep separae when possible. Ias-rising edges creae
curren spiles owing in he ground plane. These fas curren
spiles creae noise ha can corrup analog performance. Analog
and digial grounds (and supplies) should be ied a one common
ground poin o minimize circulaing digial and analog ground
currens and noise.
A high frequencies, a phenomenon called s/tn effect mus be
considered. Slin effec causes currens o ow in he ouer surfaces
of a conducorin effec maling he conducor narrower, hus
increasing he resisance from is dc value. While slin effec is
beyond he scope of his aricle, a good approximaion for he slin
deph in copper, in cenimeers, is
Slin Deph
Hz

( )
6 61 .
f

(5)
Less-suscepible plaing meals can be helpful in reducing
slin effec.
Packae|ae
Op amps are ypically offered in a variey of paclages. The paclage
chosen can affec an ampliher`s high-frequency performance.
The main inuences are parasiics (menioned earlier) and stgna/
rcuttng. Here we will focus on rouing inpus, oupus, and power
o he ampliher.
Iigure 9 illusraes he layou differences beween an op amp in
an SOIC paclage (a) and one in an SOT-23 paclage (b). Each
paclage ype presens is own se of challenges. Iocusing on
(a), close examinaion of he feedbacl pah suggess ha here
are muliple opions for rouing he feedbacl. Keeping race
lenghs shor is paramoun. Parasiic inducance in he feedbacl
can cause ringing and overshoo. In Iigures 9(a) and 9(b), he
feedbacl pah is roued around he ampliher. Iigure 9(c) shows an
alernaive approachrouing he feedbacl pah under he SOIC
paclagewhich minimizes he feedbacl pah lengh. Each opion
has suble differences. The hrs opion can lead o excess race
lengh, wih increased series inducance. The second opion uses
vias, which can inroduce parasiic capaciance and inducance.
The inuence and implicaions of hese parasiics mus be alen
ino consideraion when laying ou he board. The SOT-23 layou
is almos ideal: minimal feedbacl race lengh and use of vias;
he load and bypass capaciors are reurned wih shor pahs o
he same ground connecion; and he posiive rail capaciors, no
shown in Iigure 9(b), are locaed direcly under he negaive rail
capaciors on he boom of he board.
R
F
-V
S
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
CERAMIC
BYPASS
OPTIONAL
CAPACITOR
V
IN
DISABLE
R
G
V
OUT
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
+V
S
(a)
E
L
E
C
T
R
O
L
Y
T
I
C
B
Y
P
A
S
S
+
C
E
R
A
M
I
C
B
Y
P
A
S
S
R
L
R
F
R
G
V
OUT
-V
S
V
OUT
V
IN
+V
S
BYPASS CAPS ARE
ON BOTTOM OF BOARD
WITH GROUND RETURNS
IMMEDIATELY UNDER R
L
+V
+IN -IN
(b)
(c)
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
+V
S
R
F
-V
S
V
IN
DISABLE
R
G
V
OUT
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
CERAMIC
BYPASS
OPTIONAL
CAPACITOR
Fleure 9. Lavcut dlfferenoes fcr an cpamp olroult. (a) S0lC
paokaee. (b) S0T23. and (o) S0lC wlth R
F
underneath bcard.
Aaa|oe 0|a|oeae 30-00, Septemher (2005) 5
Lcv-dtstcrttcn amp/tfer ptncut. A new low-disorion pinou,
available in some Analog Devices op amps (he ADSu45,
1
for
example), helps eliminae boh of he previously menioned
problems; and i improves performance in wo oher imporan
areas as well. The LICSP`s low-disorion pinou, as shown in
Iigure 1u, ales he radiional op amp pinou, roaes i couner-
cloclwise by one pin and adds a second oupu pin ha serves as
a dedicaed feedbacl pin.
AD8099 DISABLE 1
FEEDBACK 2
IN 3
+IN 4
+V
S
V
OUT
C
C
V
S
8
7
6
5
Fleure 10. 0p amp wlth lcwdlstcrtlcn plncut.
The low-disorion pinou permis a close connecion beween
he oupu (he dedicaed feedbacl pin) and he invering inpu,
as shown in Iigure 11. This grealy simplihes and sreamlines
he layou.
R
F
V
O
V
IN
-V
S
DISABLE
R
L
R
G
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
+V
S
CERAMIC
BYPASS
ELECTROLYTIC
BYPASS
+
Fleure 11. lCB lavcut fcr ^D8045 lcwdlstcrtlcn cp amp.
Anoher beneh is decreased second harmonic disorion. One
cause of second-harmonic disorion in convenional op-amp pin
conhguraions is he coupling beween he noninvering inpu and
he negaive supply pin. The low-disorion pinou for he LICSP
paclage eliminaes his coupling and grealy reduces second-
harmonic disorion; in some cases he reducion can be as much
as 14 dB. Iigure 12 shows he difference in disorion performance
beween he ADSu99
2
SOIC and he LICSP paclage.
This paclage has ye anoher advanagein power dissipaion.
The LICSP provides an exposed paddle, which lowers he hermal
resisance of he paclage and can improve U
]A
by approximaely
4u%. Wih is lower hermal resisance, he device runs cooler,
which ranslaes ino higher reliabiliy.
-50
-60
-70
-80
-90
-100
-110
-120
0.1 10 1
FREQUENCY (MHz)
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
d
B
c
)
G = +5
V
OUT
= 2V p-p
V
S
= 5V
R
L
= 1006
SOIC
CSP
SOLID LINESSECOND HARMONIC
DOTTED LINESTHIRD HARMONIC
Fleure 12. ^D8099 dlstcrtlcn ocmparlscnthe same
cp amp ln S0lC and LFCSl paokaees.
A presen, hree Analog Devices high-speed op amps are
available wih he new low-disorion pinou: ADSu45, ADSu99,
and ADSuuu.
3
koat|ae aad Sh|e|d|ae
A wide variey of analog and digial signals, wih high- and low
volages and currens, ranging from dc o CHz, exiss on circui
boards. Keeping signals from inerfering wih one anoher can
be difhcul.
Recalling he advice o "Trus No One, i is criical o hinl ahead
and come up wih a plan for how he signals will be processed on
he board. I is imporan o noe which signals are sensiive and
o deermine wha seps mus be alen o mainain heir inegriy.
Cround planes provide a common reference poin for elecrical
signals, and hey can also be used for shielding. When signal
isolaion is required, he hrs sep should be o provide physical
disance beween he signal races. Here are some good pracices
o observe:
Minimizing long parallel runs and close proximiy of signal
races on he same board will reduce inducive coupling.
Minimizing long races on adiacen layers will preven
capaciive coupling.
Signal races requiring high isolaion should be roued on
separae layers andif hey canno be oally disanced
should run orhogonally o one anoher wih ground plane
in beween. Orhogonal rouing will minimize capaciive
coupling, and he ground will form an elecrical shield.
This echnique is exploied in he formaion of ccntrc//ed-
tmpedance lines.
High-frequency (RI) signals are ypically run on conrolled-
impedance lines. Tha is, he race mainains a characerisic
impedance, such as 5u ohms (ypical in RI applicaions).
Two common ypes of conrolled-impedance lines, mtcrcstrtp
4

and strtp/tne
5
can boh yield similar resuls, bu wih differen
implemenaions.
0 Aaa|oe 0|a|oeae 30-00, Septemher (2005)
A microsrip conrolled-impedance line, shown in Iigure 13,
can be run on eiher side of a board; i uses he ground plane
immediaely beneah i as a reference plane.
GROUND PLANE
DIELECTRIC H
TRACE
W
T
Fleure 13. ^ MICROSTRIP transmlsslcn llne.
Equaion 6 can be used o calculae he characerisic impedance
for an IR4 board.

Z
r
u
S7
1 41
5 9S
u S

+ ( )

]
]
]
] r .
ln
.
.
H
1 +T

(6)
H is he disance in from he ground plane o he signal race,
1 is he race widh, T is he race hiclness; all dimensions
are in mils (inches 1u
3
). d
r
is he dielecric consan of he
PCB maerial.
Sripline conrolled-impedance lines (see Iigure 14) use wo layers
of ground plane, wih signal race sandwiched beween hem. This
approach uses more races, requires more board layers, is sensiive
o dielecric hiclness variaions, and coss moreso i is ypically
used only in demanding applicaions.
EMBEDDED
TRACE
DIELECTRIC
GROUND,
POWER
PLANES
W
T
H
H
B
Fleure 14. Strlpllne ocntrclledlmpedanoe llne.
The characerisic-impedance design equaion for sripline is
shown in equaion 7.

Z
r
u
6u 1
u S
O
( )

( )
( )

]
]
]
] r
ln
.
.9
+
E
1 T

(7)
Cuard ri ngs, or "guardi ng, is anoher common ype of
shieldi ng used wih op amps; i is used o preven sray
currens f rom eneri ng sensiive nodes. The pri nciple is
sraighforwardcompleely surround he sensiive node wih a
guard conducor ha is lep a, or driven o (a low impedance)
he same poenial as he sensiive node, and hus sinls sray
currens away from he sensiive node. Iigure 15(a) shows he
guard ring schemaics for invering and noninvering op-amp
conhguraions. Iigure 15(b) shows a ypical implemenaion
of boh guard rings for a SOT-23-5 paclage.
INVERTING
GUARD
RING
NONINVERTING
GUARD
RING
(a)
INVERTING
AD8067
V
OUT
V
+IN
+V
IN
NONINVERTING
AD8067
V
OUT
V
+IN
+V
IN
(b)
Fleure 15. Cuard rlnes. (a) lnvertlne and ncnlnvertlne
cperatlcn. (b) S0T235 paokaee.
There are many oher opions for shielding and rouing. The reader
is encouraged o review he references below for more informaion
on his and oher opics menioned above.
00N0luSI0N
Inelligen circui-board layou is imporan o successful op-amp
circui design, especially for high-speed circuis. A good schemaic
is he foundaion for a good layou; and close coordinaion beween
he circui designer and he layou designer is essenial, especially
in regard o he locaion of pars and wiring. Topics o consider
include power-supply bypassing, minimizing parasiics, use of
ground planes, he effecs of op-amp paclaging, and mehods of
rouing and shielding.
I0k IukIk kA0IN0
Ardizzoni, ]ohn, "Keep High-Speed Circui-Board Layou on
Tracl, II Ttmes, May 23, 2uu5.
Brolaw, Paul, "An IC Amplifier Lser`s Cuide o Decoupling,
Crounding, and Maling Things Co Righ for a Change,
Analog Devices Applicaion Noe AN-2u2.
Brolaw, Paul and ]eff Barrow, "Crounding for Low- and High-
Irequency Circuis, Analog Devices Applicaion Noe AN-345.
Buxon, ]oe, "Careful Design Tames High-Speed Op Amps,
Analog Devices Applicaion Noe AN-257.
DiSano, Creg, "Proper PC-Board Layou Improves Dynamic
Range, IDN, November 11, 2uu4.
Cran, Doug and Sco Wurcer, "Avoiding Passive-Componen
Pifalls, Analog Devices Applicaion Noe AN-34S.
]ohnson, Howard W. and Marin Craham, Htgh-Speed Dtgtta/
Destgn, a Handbcc/ cf E/ac/ Magtc, Prenice Hall, 1993.
]ung, Wal, ed., Op mp pp/tcattcns Handbcc/, Elsevier-Newnes, 2uu5.
kIkN0S-VAlI0 AS 0I SPIN8k 2005
1
ADI websie: www.analog.com (Search) ADSu45 (Co)
2
ADI websie: www.analog.com (Search) ADSu99 (Co)
3
ADI websie: www.analog.com (Search) ADSuuu (Co)
4
hp://www.microwaves1u1.com/encyclopedia/microsrip.cfm
5
hp://www.microwaves1u1.com/encyclopedia/sripline.cfm