Pins of the XC4000E on the Xilinx Demo Board

Pins of the XC4003E, XC4010E and XC4005XL devices in a 84 PLCC package and associated connections on the Xilinx FPGA Demo Board (Original Document Developed At the University of Pennsylvania) and Bucknell Univ. The following table lists the pins numbers and names for the 84 pin XC4000 FPGA. The pins are connected to headers surrounding the socket on the demoboard. The numbers on the demoboard headers increase from the inside row to the outside, counter-clockwise. The corners at each header give the starting numbers. For a description of the FPGA Demoboard see the EE FPGA page. After configuration, any input pin that is not used will be configured as an input with a 50-100 kOhm pull-up resistor. Regular input pins will also be connected to a pull-up resistor of the same value. This is done in the IOB block on the FPGA device. The pin numbering of the 84 pin FPGA is given in the following figure. SPECS Device : XC4003E No. of Logic Gates: 3,000 No. CLB: 100 fsystem freq.: 66 MHz Delay: CLB (1.5-4.7ns, depending on the Speed grade); IOB input 2-4.8ns; IOB output (4.8-12ns). See the Xilinx
data book 2000 for more information.

XC4005XL: 5,000 logic gates; 196 logic blocks and 66MHz system clock Outputs can sink 12mA for the XC4000E and 3mA for the XC4000XL devices Figure 1: Pin numbering of the 84 pin PLCC

CHIP PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

GND VCC

Name

FPGA DEMO-BOARD Comments Ground Power supply (5V for XC4000E and 3.5V for XC40005XL) General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O

I/O (A8) I/O (A9) I/0 (A10) I/O (A11) I/O (A12) I/O (A13) I/O (A14) SGCK(A15,I/O) VCC GND PGCK1(A16,I/O) [1] I/O(A17) I/O(TDI) I/O(TCK) I/O(TMS) I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O SGCK2(I/O) [2]

Clock of external oscillator (Y1) (not on all boards available); can also used as I/O XChecker TDI (Test data in) (for boundary scan, can be reused). XChecker TCK (Test clock ) (for boundary scan, can be reused). XChecker TMS (test mode) (for boundary scan, can be reused). SW3 -1 (gen. purpose switch) SW3 -2

SW3 -3 SW3 -4 SW3 -5 SW3 -6 SW3 -7 SW3 -8 7-segment disp. U7-e

30 31 32 33 34 35 36

O(M1) GND I(MO) VCC I(M2) PGCK2(I/O) I/O(HDC)

XChecker RD/ readback, & SW2-5 ; XChecker RT/readback, & SW2-4 (Mode) SW2-6 (multiple prgrm enable) 7-segment disp. U7-d 7-segment disp. U7-c; Hi untill configuration complete. Pin is available after configuring. 7-segment disp. U7-dec. pt.; LO untill configuration complete; Pin is available after configuring. 7-segment disp. U7-b 7-segment disp. U7-a, 7-segment disp. U7-f 7-segment disp. U8-dec. pt.; XChecker INIT

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

I/O(/LDC) I/O I/O I/O I/O(/INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O SGCK3(I/O) GND DONE VCC /PROGRAM I/O(D7) PGCK3(I/O) I/O(D6) I/O(D5)

7-segment disp. U7-g 7-segment disp. U8-e 7-segment disp. U8-d 7-segment disp. U8-c 7-segment disp. U8-b 7-segment disp. U8-a 7-segment disp. U8-f 7-segment disp. U8-g XChecker DONE XChecker PROG; also SW6 (Prog. switch) SW2-7: when ON connects RST (SW4) pushbutton to pin 56 (reset to ground). LED D13 LED D14 LED D15

60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

I/O(/CS0) I/O(D4) I/O VCC GND I/O(D3) I/O(RS) I/O(D2) I/O I/O(D1) I/O(/, RDY, /BUSY) I/O(D0,DIN) SGCK4(DOUT,I/O) CCLK VCC O, TDO GND I/O(A0,/WS) I/O, PGCK4(A1) I/O(CS1,A2) I/O(A3) I/O(A4) I/O(A5) I/O (A6) I/O(A7)

LED D16 LED D9 LED D10

LED D11 LED D12

XChecker: Data IN XChecker CCLK pin not connected General I/O General I/O General I/O General I/O General I/O General I/O General I/O General I/O

NOTES: 1. PGCK 1-4: are primary global inputs wich drive each a dedicated internal global net with short delays and minimal skew. If not used, each of these pins can be a user-programmable I/O. On the demobaord PGCK1 (pin 13) can be used for an external oscillator clock input. 2. SGCK1-4: These are four secondary global inputs. . If not used, each of these pins can be a user-programmable I/O.

Reference: The Programmable Logic Data Book, Xilinx, San Jose, 1997.