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Table Of Contents

The History of Programmable Logic
Complex Programmable Logic Devices (CPLDs)
Why Use a CPLD?
Field Programmable Gate Arrays (FPGAs)
Logic Consolidation
Xilinx Devices
Xilinx CPLDs
Product Features
Selection Considerations
CoolRunner-II Architecture Description
CoolRunner-II Function Block
CoolRunner-II Macrocell
Advanced Interconnect Matrix (AIM)
I/O Blocks
I/O Banking
Design Security
XC9500XL CPLD Overview
Flexible Pin-Locking Architecture
Full IEEE 1149.1 JTAG Development and Debugging Support
Family Highlights
Platform FPGAs
Spartan-3/3E FPGAs
Spartan-3 Features and Benefits
Virtex FPGAs
Virtex-4 FPGAs
ASMBL Architecture
Inside the Virtex-4
Virtex-4 Variants
Virtex-4 LX
Virtex-4 FX
Virtex-4 SX
Military and Aerospace
Automotive and Industrial
Xilinx XA Solutions – Architecting Automotive Intelligence
Design-In Flexibility
XA Product Range
Design Tools
Schematic Capture Process
HDL Design Process
HDL File Change Example
Before (16 x 16 multiplier):
After (32 x 32 multiplier):
HDL Synthesis
ISE Software
Design Verification
Device Implementation
Place and Route
Downloading or Programming
System Debug
Dynamic Verification
Debug Verification
Board-Level Verification
Advanced Design Techniques
Embedded SW Design Tools Center
ISE WebPACK Software
Registration and Installation
Module Descriptions
Getting Started
Updating Software
Design Entry
HDL Editor
The Language Template
Edit the Counter Module
Save the Counter Module
Functional Simulation
State Machine Editor
Top-Level VHDL Designs
Simulate the Design
Top-Level Schematic Designs
ECS Hints
Creating a Top Level Schematic Design
I/O Markers
Simulating the Top Level Schematic Design
Constraints Editor
Timing Simulation
Design Challenge
Changing the Project from CoolRunner-II to Spartan-3E
The Constraints File
FPGA Reports
CPLD Reference Designs
Get the Most out of Microcontroller-Based Designs
Design Partitioning
Documentation and Example Code
Intellectual Property (IP) Cores
End Markets
Xilinx Design Services
Design Consultants
Technical Support
Glossary of Terms
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Logic Handbook

Logic Handbook

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Published by Vivekanand Upadhyay

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Published by: Vivekanand Upadhyay on Oct 18, 2011
Copyright:Attribution Non-commercial


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