ELE 704 Analog CMOS Integrated Circuits Laboratory Five - Ring Oscillators

Professor Fei Yuan September 2011

Pre-Laboratory

Voltage (current)-controlled ring oscillators are used extensively in computer systems and data communication networks. This laboratory investigates the design of fully dierential CMOS current-controlled ring oscillators. In this laboratory, you are required to design a four-stage fully dierential CMOS current-controlled ring oscillator using TSMC-0.18m 1.8V CMOS technology and analyze the performance of the designed oscillator using Spectre from Cadence Design Systems with BSIM3.3v device models. The oscillation frequency of the oscillator is 900 MHz. The delay cell of the oscillator was the originally reported in [1], as shown in Fig.1. This delay cell utilizes a positive latch formed by M12 to combat the switching noise present on the power and ground rails in the following ways : (i) The positive feedback reduces the transition time and sharpens both the rising and falling edges of the waveform of the oscillator. (ii) A fast transition minimizes the timing jitter of the oscillator. (iii) The latch eectively rejects the noise presented on the power and ground rails once the latch is established.

2
2.1

Laboratory Work
Oscillator

Design a CMOS fully dierential current-controlled ring oscillator, as per the schematic of Fig.1 where all n-well pickup contacts of pMOS transistors are connected to a clean power supply. The bond wire connecting the VDD bonding pad and the power supply pin is modeled as an ideal inductor with its inductance L = 0.1 nH. The inductance of the bond wire connecting VSS and ground is neglected so that no ground bouncing is considered. The capacitance of the bonding pads is neglected for simplicity. The width of M34 should be at least twice that of M12 in order to be able to break the positive feedback. Over-sizing M34 will result in a large capacitance at the output nodes, slowing down the oscillator. 1

VDD1 L

VDD2 L

I ctrl
Vin+ M3

M5 Vo-

M6 Vo+ Vin-

4 CL

M1

M2

M4

Cross-coupled delay cell (Stage 1)

Switching noise injector

Figure 1: Four-stage fully dierential current-controlled ring oscillator

2.2

Simulation and Analysis

Construct the symbol of the delay cell of the oscillator that has (i) two input terminals vin+ and vin , (ii) two output terminals vo+ and vo , (iii) one VDD connection terminal, (iv) one VSS connection terminal, (v) one n-well connection terminal vnwell , and (vi) one substrate connection terminal vsub , as per Fig.2.
VDD Vn-well

Vin+ Delay cell Vin-

Vo-

Vo+

VSS

Vsub

Figure 2: Symbol of the delay cell of fully dierential current-controlled ring oscillator Construct the current controlled oscillator by including (i) all delay stags, (ii) the biasing circuit, (iii) the switching noise injection circuit, and (iv) VDD and VSS circuitry including bonding wires. 2

 Perform time-domain analysis of the designed oscillator. The start of the oscillation of the oscillators can be activated by connecting a small capacitor to the output node of one of the delay stages of the oscillator with an initial voltage. Note that the value of the capacitor should be small in order to minimize the unwanted loading eect. Plot the output voltage of each stage of the oscillator with two dierent transistor widths of the latch. Measure the timing jitter. Comment on the waveform dierence. Plot the output voltage of each stage of the oscillator with two dierent control currents. Measure the rise and fall times of the output voltage in both cases. Measure the timing jitter. Comment on your ndings. Use parametric analysis and calculator tools to obtain the oscillation frequency-control current plot. Estimate the frequency tuning range and frequency control sensitivity of the designed oscillator.

Laboratory Report

A professionally prepared laboratory report containing the followings is due at the start of the next laboratory. The schematic of the current-controlled oscillator (delay cell + entire test circuit) with a boarder section showing your name and student ID. A table tabulating the exact dimension of all transistors used in your design. The waveform of the voltage of the output of each stage of the currentcontrolled oscillator with two dierent transistor widths of the latch. Measure the timing jitter at the threshold-crossing points of the output waveform of the oscillator.

 The waveforms of the voltage of the output of each stage of the currentcontrolled oscillator with two dierent control currents. Measured the rise and fall times in these two cases. Oscillation frequency - control current plot. Determine the frequency tuning range and frequency control sensitivity.

Bibliography
[1] X. Mailand, F. Devisch, and M. Kuijk, A 900 Mb/s CMOS data recovery DLL using half-frequency clock, IEEE Journal of Solid-State Circuits, vol. 37, No. 6, pp 711-715, June 2002. [2] T. Weigandt, B. Kim, and P. Grey, Analysis of timing jitter in ring oscillators, in Proc. of IEEE International Symposium on Circuits and Systems, pp. 27-30, London, 1994.