NPEC-2010

Solid State Electronic Fault Current Limiter to Limit the Fault Current in Power System
Vinod Gupta, U. C. Trivedi, N. J. Buch Electrical Research & Development Association, Vadodara-390010,
Abstract Increase in power generation capacity of electric power systems has lead to increase in the fault current level which can exceed the maximum designed short-circuit ratings of the switchgear. All the equipment therefore must have a short-circuit rating capable to withstand this level. Short-circuit currents contain extremely high energy and can damage electrical equipment. Typically, the circuit breakers open automatically in three to six cycles when a fault occurs. But circuit breakers, sometimes cannot handle the intense level of faults, as they are designed to handle designed faults current level so they fail to break and force a system to collapse. Advanced current interruption technology, utilizing high power Solid-State Fault Current Limiters (SSFCL) offers a viable solution to the transmission and distribution system problems caused by high system fault current. The SSFCL alleviates the short circuit condition in both downstream devices by limiting fault currents. To interrupt the current, SSFCL must rapidly insert an energy absorbing element (e.g. resistor) into the circuit to limit the fault current. A proper design of current limiting device will ensure that the fault current in the system is kept as low as possible in order to limit the surge current rating of the thyristor and also to minimize stresses on the power system network.

transient fault currents from becoming excessively large thus protecting a given circuit breaker to reactivate. A solid state breaker can offer the following advantages: Limited fault current. Limited inrush current (soft start), even for capacitive loads. Repeated operations with high reliability and without wear-out. Reduced switching surges. Improved power quality for healthy lines. The basic purpose of current limiter is to reduce the magnitude of the transient currents. The transient current could be either due to fault or due to switching. The need to reduce the transient current is to Reduce the thermal and mechanical stress in the system and equipment. Improve the life of switching devices. Improve power quality through mitigation of sag/swell resulting due to transient current. Types of faults: Faults can be broadly classified into two main areas which have been designated Active and Passive. Types of faults in three phase systems is shown in Fig-1

INTRODUCTION The distribution systems, especially some local distribution systems that evolved have been designed and built as the passive unidirectional systems to accept generation or bulk supplier from power grids or substations. The shortcircuit current value is limited by the impedance of various system components through which the fault currents will flow. This value and the grid section involved in the fault depend upon the interconnection of the system. Traditionally, handling these increasing fault currents often requires the costly replacement by costly substation equipment or the imposition of changes in the configuration of the system by splitting system that may lead to decreased operational flexibility and lower reliability. Consequently, with the third optional need for a current limiting device that can prevent the buildup of fault currents has been studied for years. A proper fault current limiter (FCL) would go into action very quickly and prevent the

Fig-1Types of Fault in Three phase system

(A) Phase-to-earth fault. (B) Phase-to-phase fault. (C) Phase-to-phase-to-earth fault. (D) Three phase fault. (E) Three phase-to-earth fault. (F) Phase-to-pilot fault. (G) Pilot-to-earth fault.

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The Active fault is when actual current flows from one phase conductor to another (phase-tophase) or alternatively from one phase conductor to earth (phase-to-earth). This type of fault can also be further classified into two subgroup, namely the solid fault and the incipient fault. The solid fault occurs as a result of an immediate complete breakdown of insulation. Passive faults are not real faults in the true sense of the word but are rather conditions that are stressing the system beyond its design capacity, so that ultimately active faults will occur. Typical examples are: Overloading - leading to overheating of insulation (deteriorating quality, reduced life and ultimate failure). Over voltage - stressing the insulation beyond its limits.

Under frequency - causing plant to behave incorrectly. Power swings - generators going out-ofstep or out of synchronism with each other. FAULT CHARACTERISTICS WITH & WITHOUT FAULT CURRENT LIMITER Fig-2 shows the wave shape of a typical unlimited fault current [2] as well as the influence on this wave shape if FCL devices with and without fault current interruption capability are applied to the system. A distinction among the different types of FCL is made between passive and active fault current limiting measures. Passive measures make use of already initially high source impedance both at normal and at fault conditions whereas active measures bring about a fast increase of the source impedance at fault conditions only.

Fig-2. Typical fault current wave shape and characteristic data It should be noted that instead of using fault current limiters, the problems associated with increased fault current levels can also be coped with measures like [2]: Up rating of existing switchgear and other equipment. Changes in network topology, e.g. splitting of grids or splitting of bus bars. Introduction of higher voltage levels. Use of complex control strategies like sequential tripping. PRINCIPLE OF OPERATION &TYPES OF FAULT CURRENT LIMITER: Since a fault current limiter is a series device, it must present low impedance to current flow under normal conditions. When a fault occurs, this impedance must rapidly increase to limit the current flowing into the fault. Conceptually, all types of FCL may be viewed as a normally closed switch in parallel with a resistor. The type of switch, its control circuit, and the type of resistor may vary widely from one design to another. 2

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Depending upon the method used to increase the series impedance, the current limiters can be broadly classified into the four major types: Inductive. Power electronic (EFCL). Electromagnetic. Super conductors (resistive). Electronics fault current limiter are further classified as : (1) Resistance fault current limiter: . The solid state fault current limiter concerned in this study is actually a fault current limiting and interrupting device. Fig-3 shows the configuration of a single phase FCLID. It consist of a high speed, bi directional switch realized using power semiconductor devices such as thyristor, a varistor (non linear resistor) and a snubber circuit all connected in parallel.
Varistor Snubber

collect information about the fault location and so coordinate protection replays. If the fault persists, the semiconductor devices are turned off permanently, after certain time, and the fault current is completely interrupted. (2) Resonant Circuit Current Limiters. This type of FCL limits fault current by the insertion of a resonant LC circuit with the line during a fault. The resonant LC circuit consists of an inductance and a capacitance connected either in parallel or in series, tuned to the supply frequency, 50 Hz. The impedance of this resonant circuit increases rapidly when inserted in the system and reduces the fault current. In the steady-state condition, the resonant circuit impedance is very large, theoretically infinite, if the losses are neglected. To be effective, the resonant circuit has to be inserted into the system immediately after the sensing of a fault, which is now possible with the development of power electronics switches [1]. (a) Series Resonant FCL. These type of current limiters use series tuned LC circuits connected in series in the system. The tuning frequency of the series LC circuit is chosen to be the fundamental frequency. The Thyristor-Controlled Series Resonant FCL limits fault current by the insertion of an inductor in series with the line. The resonant circuit offers very low impedance during normal steady state operations when the frequency is closer to fundamental frequency and offers very high impedance during fault conditions. This type of configuration is shown in Fig-4[1].

Supply Side

Load side

Fig-3 Resistance fault current limiter. In operation without fault, the semiconductor devices are constantly gated on. Alternatively, the whole FCLID can be bypassed using circuit breaker to avoid losses. The bypass circuit breaker is opened when the FCLID is required to operate. Consider that a short-circuit fault occurs on the load side, a semiconductor device will initially conduct the fault current. The switch is turned off when the fault current reaches a preset value Imax that should be within the interrupting capability of the semiconductor device. The fault current is thus diverted to the varistor. The clamping voltage of the varistor is set to be higher than the peak supply voltage. Therefore, the current in the faulted circuit starts to decrease. The varistor voltage remains almost constant as long as it is conducting. The semiconductor device is turned on again to reestablish the current as it reduces to a preset low value Imin. Switching logic is the same for both positive and negative half cycles of the fault current and the operation is maintained for a specific period of time which is useful to

L Supply Side

C Load side

Fig-4. Thyristor controlled Series Resonant FCL. The bus voltages are free from high frequency oscillations. However there are small voltage sags. These sags can be reduced by having large L (small C). Another effect of having large L value is the significant drop in fault currents. For the Series Reactor FCL the voltage across the FCL capacitor are approximately zero

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(short-circuit) when the thyristor switches are turned on. (b)Series-Parallel Resonant FCL. The schematic principle for the ThyristorControlled Series-Parallel Resonant FCL is depicted in Fig-5. The Series-Parallel Resonant FCL is formed by two resonant circuits tuned at the supply frequency. During normal system condition, the thyristor are not fired. The voltage drop across the FCL will be negligible since the series connected inductor and capacitor are tuned to resonate at 50 Hz. When a fault is detected, the thyristor will be turned on and the parallel resonant circuit thus formed will limit the fault current. Due to the nature of the serial circuit, the Series-Parallel FCL exhibits performance, which is very different from those of the original Resonant FCL [1].

DESIGN ANALYSIS & SIMULATION To illustrate the operating principle of resistive Electronic fault current limiter, a simulation model is simulated using MATLAB/SIMULINK for the single phase, 230V system [4] shown in fig-6 (a) & equivalent circuit with dumped parameter in fig-6 (b)

Fig-6(a) Single line diagram for distribution network

L Supply Side

C Load side

Fig-5. Thyristor-Controlled Resonant FCL.

Series-Parallel

Fig-6 (b). FCL incorporated in a distribution network Following are the Power Equipment Data:
Transformer 6.35kV//240 Volts,150 kVA, 50 Hz. Limiting Resistance 0.25 . Distribution Feeder Data:Resistance 0.00955 /km. Inductance 0.2137e-03 H/km. Capacitance 1.237e-09 F/km. Length of feeder 1 km. Load 1+j0.75 , Fault is created at the instant of 0.06 s Rated current is 256 Amps. Peak value of fault current is 2170 Amps. Limited fault current is 900 Amps.

As for the series-parallel Resonant FCL, the fault current through a Series-Parallel Resonant FCL (Fig-5) consists of a steady state, two transient and two DC components. Since the FCL is tuned to the supply frequency, the steady-state impedance will be infinite and hence the steady-state component will be zero. The transient frequency , is higher than the supply frequency, and is given by [1].
=

1 LC

L + Ls = Ls

L + Ls Ls

The bus voltages are free from high frequency oscillations. However there are slight systematic variations of the voltage envelopes, termed as voltage fluctuations. Having large FCL inductance, L (small FCL capacitance, C), the inclusion of a series resistor and small shunt capacitance value, the ranges of bus voltage fluctuations are narrower and the fault currents are lower in magnitude. On the other hand, the voltages across the FCL capacitors increase as L increases (C decreases). This increases the risk of capacitor breakdown.

Different simulated waveforms for above simulation are shown in fig-7(a) to fig-7 (e).

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Fig-7(a) C Current in feeder-1

Fig g-7(b) Curr rent in feed der-2

Fig-7(c) Voltag at point of common coupling ge g

Fig-7(d SSFCL D d) Device-1 Voltage & cu urrent

MATLAB simulink m B model Block di iagram is show in Fig-8 wn

Fig-7(e) SS SFCL Device-2 Voltag & curren ge nt

Fig-8 Simulink mo odel block diagram

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EXPER RIMENTATIO & RESU ON ULTS The res sistive SSF FCL with us sing thyrist was tor fabricated at auth hors labora atory to verify the results obtained using MA ATLAB-SIM MULINK simulati ion. Power circuit diagram & control r circuit d diagram is s shown in Fig (a) & Fig g-9 g-9(b).

The two no of CTs w T o were used to control the EFCL. One CT was u E e used for sy ynchronizat tion with supply frequency & one CT fo sensing the w or fault current. The cont f trol circuit gives pulse to g e thyristor till the normal current flow Whenever ws. fault curren exceeds the predef f nt fine setting of normal curre the circ inhibits the gate pu n ent, cuit ulse of the thyri o istor. Because the ga pulse a ate are inhibited, conducting thyristor will stop g r conducting within ha cycle of the sup c alf o pply frequency, hence fault current is diver f t rted through the resistance connected parallel to the electronic sw e witch & thu limits the fault curre us e ent. Whenever fault is cleared the circuit sta W arts giving pulse to electr g es ronic circuit. Gate driver circuit using pulse trans c g sformer was used to g give is solation be etween pow & control circuit. T wer The experimenta setup is s e al shown in the Fig-11. e

Fig-11 Expe F erimental S Setup rcuit diagra am Fig-9(a) Power cir The EFCL performa T L ance was checked by creating th c he short circuit inte ently throu ugh contactor & waveform was record c ded as sho own in Fig-10(a) & Fig-10 (b b).

Fig-9(b Control c b) circuit diagram Back to back thyristors are u o used as ele ectronic switch & resistanc in paralle to the ele ce el ectronic switch are used to limit t the fault c current. Whenev switch i OFF the current w pass ver is e will through the resista h ance connec cted paralle to the el electron switch thus limit the fault c nic current. During normal ope eration the Thyristor sw witch is conduct ting & pro ovide low impedance path. e During fault condit tion the thy yristor switc OFF ch hence f fault current is restricte dependin upon t ed ng the resistance.

Fig-10(a) lo current fault curr F oad t, rent, durati ion for shor c f circuit thro ough conta actor & ga ate pulse for th p hyristor wit positive peak faults. th

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Ishchenko, and Anton Ishchenko, 0-7803-79675/03/$i7.00 03 IEEE. [4] Harmonic Analysis and Improvement of a New Solid-State Fault Current Limiter M. M. R. Ahmed, Member, IEEE, Ghanim A. Putrus, Li Ran, Member, IEEE, and Lejun Xiao. IEEE Transactions on Industry Applications, vol. 40, no. 4, July/August 2004. [5] Simulation Study on A New Solid State Fault Current Limiter for High-Voltage Power Systems. Gang Chen, Daozhuo Jiang, Zhengyu Lu, and Zhaolin Wu, 2004 IEEE International Conference on Electric Utility deregulation, restructuring and Power Technologies (drpt2004) April 2004 Hong kong. [6] A New Proposal for Solid State Fault Current Limiter and Its Control Strategies. Gang Chen, Daozhuo Jiang, Zhengyu Lu, and Zhaolin Wu. [7] 3-Phase Fault Current Limiter for distribution systems Vijay K. Sood, Fellow, IEEE, and Shahabur Alam. 0-7803-9772-X/06/$20.00 2006 IEEE. [8] Case study of HTS resistive superconducting fault current limiter in Electrical distribution systems. Lin Ye, A.M. Campbell, ELSEVIER, Electric Power Systems Research 77 (2007) 534539. [10] CIGRE WG 13.10: Functional Specification for a Fault Current Limiter. ELECTRA (2001) 194, pp. 22-29. (http://www.cigre.org)

Fig-10(a) load current, fault current, duration for short circuit through contactor & gate pulse for thyristor with positive peak faults. CONCLUSION The single phase resistive EFCL using MATLB was simulated. The results obtained through simulation were verified through experiment & are matching with the simulation results. Resistive EFCL can limit the fault current with half cycle. For large scale implementation series resonance EFCL are more advantageous as it can restrict the fault current much faster than resistive EFCL.

ACKNOWLEDGEMENT Author would like to give their sincere thanks to Dr. M. Rammoorty Ex-Director Electrical Research & Development Association, for his guidance for carrying out this research work at ERDA. REFERENCES [1] Design Synthesis of Resonant fault current Limiter for Voltage Sag mitigation and Current Limitation, C. S. Chang, Member, IEEE, P. C. Loh, Student Member, IEEE, [2] Fault current limiters application, principles and experience, CIGRE WG A3.16: H. Schmitt*, J. Amon, D. Braun, G. Damstra, K.-H. Hartung, J. Jger, J. Kida, K. Kunde, Q. Le, L. Martini,M. Steurer, Ch. Umbricht, X. Waymel and C. Neumann. [3] Solid-state Fault Current Limiter for Medium Voltage Distribution Systems. Boris Korobeynikov, Member, IEEE, Dmitry