Ict123 W3

Centre for Computer Technology
ICT123 Computer Architecture

Week 03
Integer and Floating Point

Data processing
Content at a Glance
Week 2 Review Integer data representation/Interpretation Integer data addition and subtraction Integer data limitation Floating Point data IEEE754 Standard Floating Point data Arithmetic
March 20, 2012
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Von Neumann Architecture
Most computers are based on the Von Neumann architecture concepts developed by John Von Neumann in the mid 1940s.
1.
2.
Locn 410
Locn 414 Locn 416
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Instrcn 1 Instrcn 2 Instrcn 3

Memory
3.
The 3 key concepts in Von Neumann architecture are: Data and instructions are stored in a single read/write memory The contents of this memory are addressable by location, regardless of its contents Instructions are executed in a sequential manner, one after another; in a single processing unit.
Von Neumann Architecture
The Von Neumann bottleneck The speed of a von Neumann computer is limited by the fact that instructions and data must be accessed sequentially via a single bus
March 20, 2012
Harvard Architecture
Harvard architecture machines have separate program and data memories, with their own separate busses. Thus Harvard machines are potentially faster, as we can access the next instruction while fetching the data for the current instruction
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Instruction Cycle State Diagram
March 20, 2012
Instruction cycle with interrupts

Interrupts Enabled
Handle Interrupt Request (Switch task) Check for Interrupt s

Interrupts Enabled
Interrupts Disabled START
IF
EI
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STOP
Computer architectures are closely related to what their instructions may be able to do, and may be categorised as:
Zero Address One address Two Address and Three Address
Machine organization and instruction sets
architectures.
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Observation
The simpler the architecture:
the simpler the instruction set i.e. supports only simple, short and therefore fast instruction. requires a longer and more complex program the shorter the program, but requires support for more complex instructions
The wider the address architecture:
March 20, 2012
Integer data representation

All integer data is represented by a fixed length bit (Binary digit) sequence. Computers are designed to handle integer numbers in byte (8-bit) lots e.g. byte ( or octet ) 8 bits word 16 bits (2 bytes) long (or double) word 32 bits (4 bytes or 2 words) quad word 64 bits (4 words or 8 bytes) Most current programming languages like Java, handle integer data as a 32-bit quantity by default
March 20, 2012
Integer data interpretation

The machine does not care about nor does it attempt to interpret the data it holds. It is the programmers responsibility to interpret the stored bit pattern data. However, the machine provides support to enable signed and unsigned interpretation all processed data.
March 20, 2012
Consider the following
Integer data interpretation

4 bit pattern
0010 0110 1110 2 6 -2 [ or 14 ]
8 bit pattern
0000 0010 0000 0110 1111 1110 2 6 -2 [or 254]
Unsigned : ki x 2i , for 0 i n-1 Signed

March 20, 2012
: - kn-1 x 2n-1 + ki x 2i , for i = 0 to (n-2)

Geometric Depiction of Twos Complement Integers
March 20, 2012
Integer data addition
For simplicity we will use 4 bit numbers to illustrate the operations 6 2 --8 0110 0010 ------1000
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Integer data subtraction
so
A B = A + [ -B ] i.e. 2s comp addition 6 -2 --4 0110 0010 becomes ------0100

6 + [-2] ---4
0110 1110 ------0100
March 20, 2012
Two negative Numbers -9 10111 -4 11100 1 10011
Equal and Opposite Numbers

-9 10111 +9 01001 0 100000
Disregard; the result is 00000(sum = +0)
Positive Number and Larger Negative Number
Positive Number and Smaller Negative Number +9 0 1001 (augend)
-9 10111 +4 00100 11011
-4 1 1100 (addend)
(sum = -5) 1 0 0101
Sign bits
This carry is disregarded; the result is 01001(sum=+5)
Negative sign bit

March 20, 2012
Multiplication Example

1011 x 1101 1011 0000 1011 1011 10001111

March 20, 2012
Multiplicand (11 dec) Multiplier (13 dec) Partial products Note: if multiplier bit is 1 copy multiplicand (place value) otherwise zero Product (143 dec)
Note: need double length result

Division of Unsigned Binary Integers

00001101 1011 10010011 1011 001110 Partial 1011 Remainders 001111 1011 100 Divisor Quotient Dividend
Remainder
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Division of Unsigned Binary Integers

00001101
1011 10010011 1011 001110 Partial 1011 Remainders 001111 1011 100 Divisor
March 20, 2012
Quotient Dividend
Remainder
Simple Integer Unit
(CSA, Frank Duyker)

March 20, 2012
Integer data limitation
Range
bits n 8 16 32 64
March 20, 2012
unsigned 2n - 1 0 to 255 0 to 65,535 4.2949 * 109 1.84467 * 1019
signed (2sComp) -2n-1 to + (2n-1 - 1) - 128 to +127 -32768 to +32767 2.14748 * 109 9.223 * 1018
Floating Point data
Floating point data representation allow us to store fractional numbers, and is modelled on scientific notation. e.g.1: (+) 3.5 * 102 [ 350 ] e.g.2: - 25 * 10-3 [ - 0.025 ] We can store floating point numbers in three parts, namely: sign, significand, exponent The same applies to binary numbers
March 20, 2012
Single precision numbers are stored in 32-bit normalized binary format:

msb
IEEE754 Standard
lsb
8 bits biased exponen t
23 bits Significand In a normalized binary number the msd is 1, which is implied (not stored).
March 20, 2012
Sign of significand 0 positive 1 negative
Biased Exponent
Add 127 for single precision (1023 for double precision) All possible exponents from -127 to +127 convert into unsigned numbers from 0 to 255. Examples: If the exponent is 4, the exponent field will be 4+127 = 131 (10000011). If exponent contains 01011101 (93), the actual exponent is 93-127 = -34. Easy to compare magnitudes like unsigned integers.
March 20, 2012
Significand
The significand represents a binary fraction. There is an implicit 1 to the left of the binary point. For example, for the significand 01101..., the actual mantissa would be 1.01101... There is exactly one non-zero digit to the left of the point.
March 20, 2012
Converting 347.625 to IEEE 754 format

1. Convert this to binary: 347.625 = 101011011.101 2. 2. Normalize the number by shifting the binary point until there is a single 1 only to the left: 101011011.101 x 2 0 = 1.01011011101 x 2 8 3. The digits to the right of the binary point, 010110111012, comprise the significand. 4. The number of times you shifted gives the exponent. In this example, it was shifted 8 places to the left. The exponent field contains; 8 + 127 = 135 = 100001112. 5. The number is positive, so the sign bit is 0.
6. IEEE format: 0 10000111
March 20, 2012
01011011101000000000000
Question
Convert (479.75)10 to 32 bit IEEE 754 floating point format.
March 20, 2012
Single precision number

Examples:

2 10 1.00 * 21 Exp = 128; Sig = 0 1 01 1.00 * 20 Exp = 127; Sig = 0 0.5 0.1 1.00 * 2-1 Exp = 126; Sig = 0 10 1010 1.01 * 23 Exp = 130; Sig = 010...0 0 0.00 ?? Special case Exp = Sig = 0
March 20, 2012
Single Precision Number range

Negative numbers between - (2 2-23 ) x 2128 to -2-127 Positive numbers between 2-127 to (2-2-23) x 2128
There is a small number range near (and including) zero which cannot be represented in the normalized format. This is known as underflow. Zero is treated as a special case
March 20, 2012
Special Cases

Negative numbers less than -(2 - 2-23) x 2128, called negative overflow. Negative numbers greater than -2-127, called negative underflow. Zero Positive numbers less than 2-128, called positive underflow. Positive numbers greater than (2 - 2-23) x 2128, called positive overflow.
March 20, 2012
Expressible Numbers
(Stallings p.310)
March 20, 2012
IEEE754 Standard
Double precision numbers are stored in 64-bit normalized binary format: msb
lsb
11 bits biased exponen t
52 bits Significand In a normalized binary number the msd is 1, which is implied (not stored).
March 20, 2012
Sign of significand 0 positive 1 negative
IEE 754 FPN Interpretation

Interpretation of IEEE 754 Floating-Point Numbers Single Precision (32 bits) Biased Sign exponent Fraction Value Positive zero Negative zero Plus infinity Minus infinity NaN Positive normalized non-zero Negative normalized non-zero Positive denormalized non-zero Negative denormalized non-zero 0 1 0 255 (all 1s) 1 255 (all 1s) 0 or1 255 (all 1s) 0 0 0 0 0 0 0 0 Double Precision (64 bits) Biased Sign exponent Fraction Value 0 1 0 0 0 0 0 0 not 0 NaN 0 0
0 2047 (all 1s) 0 2047 (all 1s) 0 or1 2047 (all 1s)
not 0 NaN
0 0 < e < 255
2e-127 (1.f)
0 0 < e < 2047 f
2e-1023 (1.f)
1 1 < e < 255
-2
e-127
(1.f)
1 1 < e < 2047 f
-2
e-1023
(1.f)
0 f <> 0
2e-126 (0.f)
0 f <> 0
2e-1022 (0.f)
March 20, 2012
0 f <> 0
-2
e-126
(0.f)
0 f <> 0
-2
e-1022
(0.f)
(Stallings, p.313)
Floating Point data Arithmetic
Floating point arithmetic operations performed by numeric data processors (co-processors) are: addition subtraction multiplication and division
March 20, 2012
Floating Point Addition and subtraction

In addition and subtraction it is necessary to have both operands with the same exponent value
The steps in are:
1. 2.
3.
4.
check for zero values denormalize significant and equalize exponent values add/subtract the significant values normalize the result
March 20, 2012
Addition - Example

99.99 + 0.161 = 100.151 Denormalize the numbers 9.999 x 101 1.610 x 10-1 Equalize Exponents 1.610 x 10-1 = 0.0161 x 101
Add the Significands 9 .9990 x 101 + 0.0161 x 101 10 .0151 x 101

March 20, 2012
Subtraction - Example
99.99 - 0.161 = 99.829 Denormalize the numbers 9.999 x 101 1.610 x 10-1 Equalize Exponents 1.610 x 10-1 = 0.0161 x 101 Add the Significands 9 .9990 x 101 - 0.0161 x 101 9.9829 x 101
March 20, 2012
FP Addition & Subtraction Flowchart
March 20, 2012
Floating Point multiplication and division
Floating point multiplication and division are simpler than addition and subtraction because the is no need to align exponents
1. 2. 3. 4. 5. 6.
The steps in are: check for zero values add/subtract exponents check for errors multiply/divide significands normalize round
March 20, 2012
Multiplication - Example
To multiply two values, first multiply their magnitudes and add the exponents. 9.999 x 101 x 1.610 x 10-1 16 .098 x 100
The sign of a product is the xor of the signs of the operands.
March 20, 2012
Division - Example
To multiply two values, first divide their magnitudes and subtract the exponents. 9.999 x 101 1.610 x 10-1 6 .210 x 102
The sign of a product is the xor of the signs of the operands.
March 20, 2012
Floating Point Multiplication
March 20, 2012
Floating Point Division
March 20, 2012
Floating Point Unit
(CSA Frank Duyker)

March 20, 2012
Guard bits and Rounding
all arithmetic operations suffer from rounding errors rounding errors occur because we cant represent all values exactly, so we approximate their values
guard bits are additional bits attached to the rhs of the significand guard bits help to retain accuracy in the final result
March 20, 2012
NaN
NaN is a symbolic quantity encoded in floating point numbers for a result which can not be represented in the available space or format e.g. result, or meaningless result from 0/0, / , or 0*
March 20, 2012
Floating Point Hardware
Intel introduced the 8087 coprocessor around 1981.

Intels 80486, introduced in 1989, included floating-point support in the processor itself.
(Ravi, Haritha, Vasuki, Satish- Floating Point Architecture, July 2007)
The main CPU would call the 8087 for floatingpoint operations. The 8087 had eight special 80-bit (extended precision) registers that could be accessed in a stack-like fashion. Some of the IEEE standard is based on the 8087.
March 20, 2012
Reference
Stallings William, 2003, Computer Organization & Architecture designing for performance, 7th edn, Pearson Education,Inc [Chapter 9] Ravi Paruchuri, Haritha Talluri, Vasuki Mulukutla, Satish Gogisetty - Floating Point Arithmetic Computer Systems Architecture, Frank Duyker. C S 465 Computer Organisation
March 20, 2012
relevant web sites

http://www.rwc.uc.edu/koehler/comath/text.html ftp://shell.shore.net/members/w/s/ws/support/Num berSystems.pdf http:/docs.sun.com/source/8063568/ncg_goldberg.html http://grouper.ieee.org/groups/754/
March 20, 2012

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Centre for Computer Technology

ICT123 Computer Architecture

Integer and Floating Point

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Von Neumann Architecture

Instrcn 1 Instrcn 2 Instrcn 3

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Von Neumann Architecture

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Instruction Cycle State Diagram

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Instruction cycle with interrupts

Handle Interrupt Request (Switch task) Check for Interrupt s

Interrupts Disabled START

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Machine organization and instruction sets

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

The simpler the architecture:

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

The wider the address architecture:

March 20, 2012

Integer data representation

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Integer data interpretation

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Consider the following

Integer data interpretation

Unsigned : ki x 2i , for 0 i n-1 Signed

: - kn-1 x 2n-1 + ki x 2i , for i = 0 to (n-2)

Geometric Depiction of Twos Complement Integers

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Integer data addition

March 20, 2012

Integer data subtraction

A B = A + [ -B ] i.e. 2s comp addition 6 -2 --4 0110 0010 becomes ------0100

0110 1110 ------0100

March 20, 2012

Two negative Numbers -9 10111 -4 11100 1 10011

Equal and Opposite Numbers

Disregard; the result is 00000(sum = +0)

Positive Number and Larger Negative Number

Positive Number and Smaller Negative Number +9 0 1001 (augend)

-9 10111 +4 00100 11011

Negative sign bit

1011 x 1101 1011 0000 1011 1011 10001111

Note: need double length result

Division of Unsigned Binary Integers

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Division of Unsigned Binary Integers

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Simple Integer Unit

(CSA, Frank Duyker)

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute