ICT123 Computer Architecture: Week 05 CPU Micro-Operations and Control Details

Centre for Computer Technology
ICT123 Computer Architecture

Week 05
CPU Micro-operations and Control details
Content at a Glance
Week 4 System architecture and system operation review
Micro-operations Control unit architecture and operation
March 20, 2012
Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
Bus Interconnection Schemes

Single System Bus
March 20, 2012
CPU Internal Structure
March 20, 2012
Computer Components: Top Level View
March 20, 2012
Recall that computer instructions consist of sequential parts such as FI, DI, OF EI Each of these parts in turn has 1 or more steps e.g. FI: - calculate instruction address - load instruction to IR OF: - calculate operand address - load data unit
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Micro-Operations (1)
Micro-operations (-ops) are the atomic (indivisible) operations performed by the CPU (CU). By definition -ops are very small, simple instruction steps that are performed by the control unit (CU) in a single clock cycle. -ops are very efficient but they accomplish very little
March 20, 2012
Registers (R)
ALU (f)
1 machine cycle
R3 f(R1, R2)
f: shift, load, clear, increment, add, subtract, complement, and, or, xor,
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(Register Tarnsfer and Micro-Operations) Richard Salomon, Sudipto Mitra Copyright Box Hill Institute
March 20, 2012
Fetch Cycle Instruction is fetched from memory (MAR, MBR, PC, IR)

T1: MAR T2: MBR PC T3: IR
(PC) Memory (PC) + I (MBR)
Indirect Cycle Fetch source operands

T1: MAR T2: MBR T3: IR (Address)
(IR (Address)) Memory (MBR (Address))
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Interrupt Cycle A test is made to determine if any of the enabled interrupts have occurred.
T1:
MBR (PC) T2: MAR Save_Address PC Routine_Address T3: Memory (MBR)
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Execute Cycle The execute cycle will have a number of sequences of microoperations.
For example ADD R1, X

T1:
MAR T2: MBR T3: R1

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(IR (Address)) Memory (R1) + (MBR)

e.g.
1. FI
Micro-Operation Examples
e.g. 2. add R1 , [X]
e.g. 3. djz d, R2
t1: MAR (PC) t2: MBR ((PC)) t3: IR (MBR)
t1: MAR (IR(address)) t2: MBR (X) t3: R1 (R1) + (MBR) [ ] indicates indirect mode
t1: MAR
(IR(address)) t2: MBR (R2) t3: MBR (MBR) - 1 t4: R2 (MBR) if (MBR) = 0 then PC (PC) + d
() read: contents of
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Flowchart for H/W Instruction Cycle
March 20, 2012
A Simple CPU -OP Example
To illustrate the relationship between the -op and the -instruction, we now consider a simple hypothetical CPU as follows:
March 20, 2012
A Simple CPU with Common ALU

R1 R2 Sel A R7
1 OF 8 Decoder
Input
MuxA
MuxB
Sel B
Sel D
ALU
Oprn
Control word: Oprn SelD SelA SelB
Output
March 20, 2012
ALU Control Codes

Binary Code 00 00 00 00 00 01 01 01 01 10 11 000 001 010 101 110 000 010 100 110 000 000 Hex Code 00 01 02 05 06 08 0A 0C 0E 10 18 Operation Transfer A Increment A A+B AB Decrement A A and B A or B A xor B Complement A Shift A right by 1 bit Shift A left by 1 bit Mnemonic TRFA INCA ADD SUB DECA AND OR XOR COMA SHAR SHAL
March 20, 2012
Select Fields Control Codes

Binary Code 000 001 010 011 100 101 110 111
March 20, 2012
Sel D Output R1 R2 R3 R4 R5 R6 R7
Sel A Null R1 R2 R3 R4 R5 R6 R7
Sel B Input R1 R2 R3 R4 R5 R6 R7
Micro - instruction example

R1 R2 - R3 Control word form: OPRN Sel D Sel A Sel B SUB R1 R2 R3 Control word: 00101 001 010 011 or 0x0A53
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Structure - Control Unit

Control Unit
CPU
ALU Internal Bus Registers Control Unit
Sequencing Logic Control Unit Registers and Decoders
Control Memory
March 20, 2012
Functional Requirements of the CU

1. 2.
3.
Define the basic elements of the processor Describe the micro-operations that the processor performs. Determine the functions that the control unit must perform to cause the micro-operations to be performed.
March 20, 2012
Control Unit Design (1)

Micro-operations are broadly classified into one of the following categories
Transfer data from one register to another Transfer data from a register to an external interface (e.g. system bus) Transfer data from an external interface to a register Perform an arithmetic or logic operation, using registers from input and output.
March 20, 2012
Control Unit Design (2)

The control unit performs two basic tasks Sequencing step through a series of micro-operations in the proper sequence Execution cause each micro-operation to be performed
March 20, 2012
Model of Control Unit
March 20, 2012
Control Unit Signals
Input Signals

Clock Instruction Register Flags Control Signals from control bus
Output Signals
Control signals within the processor (e.g. data transfer between registers, specific ALU functions) Control signals to control bus (e.g. memory, I/O modules) March 20, 2012 Richard Salomon, Sudipto Mitra
Copyright Box Hill Institute
Control Signals
Three types of control signal

Signals
that activate an ALU function Signals that activate a data path Signals on the external system bus or other external interface. All signals are applied as binary inputs to individual logic gates.
March 20, 2012
Example Control Signal Sequence Fetch (1)
MAR <- (PC)
Control unit activates signal to open gates between PC and MAR
MBR <- (memory)

Open gates between MAR and address bus Memory read control signal Open gates between data bus and MBR Increment PC and store it
March 20, 2012
Example Control Signal Sequence Fetch (2)
CU sends a control signal to open gates between MBR and IR. Check whether to perform an Indirect Cycle or Execute Cycle by examining the IR for an indirect memory reference. (Examine the IR for indirect cycle and interrupt cycles)
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Example Control Signal Sequence - Execute

Examine the opcode Determine which sequence of microoperations to perform
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Data Paths and Control Signals
March 20, 2012
Internal Organization
Usually a single internal bus Gates control movement of data onto and off the bus Control signals control data transfer to and from external systems bus Temporary registers needed for proper operation of ALU
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MicroOperations Fetch
Timing T1: MAR PC T2: MBR Memory PC PC + 1 T3: IR MBR T1: MAR IR (Address) T2: MBR Memory T3: IR (Address) Memory (Address)
Active Control Signals C2 C5, CR C4 C8 C5, CR C4 C1
Indirect
Interrupt T1: MBR PC T2: MAR Save Address PC Routine Address March 20, 2012 Richard Salomon, Sudipto Mitra T3: Memory MBR Hill Institute Copyright Box
C12, CW
CPU with Internal Bus (Addition)

T1: MAR IR (Address) T2: MBR Memory T3: Y MBR T4: Z AC + Y T5: AC Z
March 20, 2012
Control Unit Design

The CU can be implemented either as a hardwired circuit known as hardware implementation, or in programmed form referred to as micro-programmed implementation Early computers employed hardware implemented CUs Most computers now use microprogrammed CU implementation
March 20, 2012
Intel 8085 OUT Instruction Timing Diagram
March 20, 2012
Hardwired Implementation (1)

Control unit inputs Flags and control bus
Each bit means something Op-code causes different control signals for each different instruction Unique logic for each op-code Decoder takes encoded input and produces single output n binary inputs and 2n outputs
Instruction register

March 20, 2012
Hardwired Implementation (2)
Clock
Repetitive sequence of pulses Useful for measuring duration of micro-ops Must be long enough to allow signal propagation Different control signals at different times within instruction cycle Need a counter with different control signals for t1, t2 etc.
March 20, 2012
Control Unit with Decoded Inputs
March 20, 2012
Problems With Hard Wired Designs

Complex sequencing and micro-operation logic Difficult to design and test Inflexible design Difficult to add new instructions
March 20, 2012
Micro-programmed Control Organization

Next Address Generator (Sequencer) Control Address Register Control Data Register
External
Input
Control Memory
Control Word
Next Address Information
March 20, 2012
Micro-programmed Control Unit Design (1)
The CU is implemented as a sequence of micro-instructions which are converted into a set of control signals based on the binary pattern of the control word Each signal value corresponds to the binary value of their respective control word bit.
control word signals
March 20, 2012

We sequence the control words in memory as a group of -instructions The -instruction is formed by adding control bits and the address of the next -instruction to the control word. This forms a horizontal -instruction
control word
March 20, 2012
control bits
address
March 20, 2012

A shorter -instruction results if instead of generating all signals directly a code for the signals is produced, which is fed into a decoder which produces the control signals. This results in a vertical -instruction unit.
March 20, 2012
(Stallings p.604)
(Stallings p.604)
March 20, 2012
Control Unit Function

Sequence logic unit issues read command Word specified in control address register is read into control buffer register Control buffer register contents generates control signals and next address information Sequence logic loads new address into control buffer register based on next address information from control buffer register and ALU flags
March 20, 2012
Next Address Decision
Depending on ALU flags and control buffer register

Get next instruction (Add 1 to control address register) Jump to new routine based on jump microinstruction (Load address field of control buffer register into control address register) Jump to machine instruction routine (Load control address register based on opcode in IR) Richard Salomon, Sudipto Mitra
Copyright Box Hill Institute
March 20, 2012
CU Implementation Pros and Cons
Hardwired very complex even for simple architecture CPUs can be difficult to implement inflexible fast (h/w speed) execution
March 20, 2012
Micro- programmed easier to implement simple design flexible takes a computer architecture form flexible significant address generation time and -instruction size
Micro-programming Applications

Almost all CUs in current CPUs are micro-programmed units A few examples of micro-programming applications are: emulation of one CPU by another provision of specific operating system support by implementing primitives that replace parts of the OS HLL support by implementing various functions and data types micro-diagnostics to monitor, detect and isolate system errors
March 20, 2012
Reference
Stallings William, Computer Organization and Architecture Designing for performance, 7th edn, Pearson Education.Inc, ISBN 0 - 13 185644 - 8 [ Chapter 16 & 17 ] M Morris Mano, Computer System Architecture, 3rd edn, Prentice Hall, ISBN 0 - 13 - 175563 - 3 [ Chapter 7 ]
March 20, 2012

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Centre for Computer Technology

ICT123 Computer Architecture

CPU Micro-operations and Control details

Week 4 System architecture and system operation review

Micro-operations Control unit architecture and operation

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Bus Interconnection Schemes

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

CPU Internal Structure

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Computer Components: Top Level View

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

T1: MAR T2: MBR PC T3: IR

(PC) Memory (PC) + I (MBR)

Indirect Cycle Fetch source operands

T1: MAR T2: MBR T3: IR (Address)

(IR (Address)) Memory (MBR (Address))

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

MBR (PC) T2: MAR Save_Address PC Routine_Address T3: Memory (MBR)

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

For example ADD R1, X

MAR T2: MBR T3: R1

(IR (Address)) Memory (R1) + (MBR)

e.g. 2. add R1 , [X]

t1: MAR (PC) t2: MBR ((PC)) t3: IR (MBR)

March 20, 2012

Flowchart for H/W Instruction Cycle

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

A Simple CPU -OP Example

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

A Simple CPU with Common ALU

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

ALU Control Codes

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Select Fields Control Codes

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Micro - instruction example

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Structure - Control Unit

Sequencing Logic Control Unit Registers and Decoders

March 20, 2012

Richard Salomon, Sudipto Mitra Copyright Box Hill Institute

Functional Requirements of the CU

March 20, 2012

Control Unit Design (1)

March 20, 2012