Ch7 Sequential

Chapter 7
Sequential Circuits
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
August 20, 2004; Revised - July 4, 2005
B.Supmonchai
Goals of This Chapter
Implementation techniques for

Register: latches and flipflops Schmitt Triggers Oscillator, pulse generators
Static versus Dynamic Realization

Clocking Strategies
2102-545 Digital ICs
Sequential Logic
B.Supmonchai
Sequential Logic
Inputs Outputs
COMBINATIONAL LOGIC
Current State
Q
Next state
State Register
CLOCK
Storage Mechanisms Positive Feedback STATIC

Charge-Based DYNAMIC
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Sequential Logic
B.Supmonchai
Static vs Dynamic Storage
Static storage
preserve state as long as the power is on have positive feedback (regeneration) with an internal
connection between the output and the input

useful when updates are infrequent (clock gating)
Dynamic storage
store state on parasitic capacitors only hold state for short periods of time (milliseconds)
require periodic refresh

usually simpler, so higher speed and lower power
Sequential Logic
B.Supmonchai
Latches versus Flipflops
Latches (with Clock)

level sensitive circuit that passes inputs to Q when the clock is
high (or low) - transparent mode

input sampled on the falling edge of the clock is held stable
when clock is low (or high) - hold mode
Flipflops (edge-triggered)
edge sensitive circuits that sample the inputs on a clock
transition
positive edge-triggered: 0 1 negative edge-triggered: 1 0
built using latches (e.g., master-slave flipflops)
Sequential Logic
B.Supmonchai
Review: The Regenerative Property

Vi1 Vo1 Vi2 Vo2
Cascaded Inverters
Small deviation from bias point C (e.g., from noise) is amplified and regenerated around the circuit loop until either point A or B is reached If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point.
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C B Vi1 = Vo2
Sequential Logic
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Review: Bistable Circuits
The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)
Vi1 Vi2
Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1
done by applying a trigger pulse at Vi1 or Vi2 the width of the trigger pulse need be only a little larger than
the total propagation delay around the loop circuit (twice the delay of an inverter)
Sequential Logic
B.Supmonchai
Review: SR Latch
!Q
S 0
R 0
Q Q
!Q !Q
Action memory
1
R Q 0 1
0
1 1
1
0 0
0
1 0
set
reset disallowed
Sequential Logic
B.Supmonchai
Review: Clocked D Latch

D !Q
D Q clock transparent mode
clock
clock hold mode

In our course All latches mean clocked latches

Sequential Logic
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Latches versus Flipflops II
Latch stores data when clock is low (high)

D Q Clk
Flipflop stores data when clock rises (falls)

D Q Clk
Clk D Q
Clk
D
Q
Sequential Logic
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B.Supmonchai
Positive and Negative Latches

Positive Latch In
D G Q
Negative Latch Out In

D G Q
Out
Clk
Clk
Clk In Out
Out Stable
Clk
In Out
Out Follow In Out Stable Out Follow In Out Stable
Out Follow In
Out Stable
Out Follow In 11
Sequential Logic
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Latch-Based Design
N latch is transparent when f = 0 P latch is transparent when f = 1
N Latch
Logic
P Latch
Logic
Sequential Logic
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Timing Metrics
clock tsu In thold
clock
time
data stable
tc-q
time
output stable
Out
output stable
Sequential Logic
time
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Timing Definitions
Setup time, tsetup is the time that the data inputs (D) must be valid before the clock transition
0 to 1 transition for a positive edge-triggered device 1 to 0 transition for a negative edge-triggered device
Hold time, thold is the time that the data inputs must remain valid after the clock edge Propagation Delay, tc-q is the worst case propagation delay (with reference to the clock edge)
time to copy D to Q
Sequential Logic
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System Timing Constraints

Inputs Outputs
COMBINATIONAL LOGIC
Current State
Q
Next state
State Register
T (clock period)
CLOCK
tcd: contamination delay = minimum delay
tcdreg + tcdlogic thold

T tc-q + tplogic + tsu

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Sequential Logic
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Notes on System Timing Constraints
It is important to minimize the values of the timing parameters associated with the register.
In modern high-performance systems, the register propagation delay and set-up times account for a significant portion of the clock period.
DEC Alpha EV6 has a maximum logic depth of 12 gates and
the register overhead accounts for about 15% of the clock period.
Hold time becomes an issue when there is little logic between registers or when the clocks at different registers are somewhat out of phase due to clock skew.
Sequential Logic
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Building A (Static) Latch

For a latch, use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
CLK
CLK
Q CLK
D CLK
CLK
can implement as NMOS-only Overpowering the feedback loop (as in Static RAM)
Sequential Logic
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Cutting the feedback loop (Mux-based latch)

B.Supmonchai
MUX Based Latches
Change the stored value by cutting the feedback loop

feedback feedback
1 Q D 0 clk Negative Latch Q = clk & Q | !clk & D transparent when the clock is low
0 Q D 1 clk Positive Latch Q = !clk & Q | clk & D transparent when the clock is high
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Sequential Logic
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TG MUX Based Latch Implementation

clk Q !clk D clk clk load is two transistors (and two for !clk) = clock load of 4 Having to generate both clk and !clk (nonoverlapping clocks)
Positive Latch
input sampled (transparent mode)
clk !clk
feedback (hold mode)

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Sequential Logic
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PT MUX Based Latch Implementation

clk !Q
Q
input sampled (transparent mode) !clk clk
Reduced clock load, but threshold drop at output of pass transistors so reduced noise margins and performance
!clk
feedback (hold mode)

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Sequential Logic
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Latch Race Problem

B
clk
clk T tc-q + tplogic + tsu Thigh tc-q + tcdlogic

Which value of B is stored?
Two-sided clock constraint

Sequential Logic
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Master Slave Based ET Flipflop

D 0 1 D 0 clk Master QM Q clk Q
clk
clk
Slave D QM Q
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clk = 0 clk = 1
transparent hold
hold transparent
Sequential Logic
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MS ET Implementation
Master Slave
I2
T2
I3
I5
T4
I6
QM D
clk
I1
T1
I4
T3
20 Transistors* 8 clock loads

* Ignore clk buffer
master transparent slave hold clk !clk

master hold slave transparent
Sequential Logic
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MS ET Timing Properties
Assume propagation delays are tpd_inv and tpd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0 Set-up time - time before rising edge of clk that D must be valid
tsu = 3 * tpd_inv + tpd_tx
Propagation delay - time for QM to reach Q

tpd = tpd_inv + tpd_tx
Hold time - time D must be stable after rising edge of clk

thold = 0
Sequential Logic
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Notes on MS ET Timing Properties
Set-up time
How long before the rising edge does D have to be stable such
that QM samples the value reliably?

D has to propagate through I1, T1, I3 and I2 before the rising
edge to ensure that the node voltages on both terminals of T2 are the same value.
Propagation delay time

Since the delay of I2 is included in the set-up time, the output
of I4 is valid before the rising edge of clk, so the delay is simply the delay through T3 and I6
Hold time
since T1 turns off when the clock goes high, any changes in D
after clk goes high are not seen, so hold time is 0

Sequential Logic
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Set-up Time Simulation

3 2.5 2
Q QM D
Volts
1.5 1
tsetup = 0.21 ns
clk
I2 out
0.5
0
-0.5 0 0.2 0.4 0.6 0.8 1
Time (ns)
works correctly
Sequential Logic
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B.Supmonchai
Set-up Time Simulation II

3 2.5 2
Q I2 out D clk QM
0 0.2 0.4 0.6 0.8 1
Volts
1.5 1 0.5 0
tsetup = 0.20 ns
-0.5
Time (ns)
Fails!
the clock is enabled before the nodes on both sides of the transmission gate T2 settle to the same value
Sequential Logic
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Propagation Delay Simulation

3 2.5 2
tc-q (LH) = 160 psec
tc-q (HL) = 180 psec
Volts
1.5
Clk
1
0.5 0 -0.5
tc-q (LH)
tc-q (HL)
0.5
1.5
2.5
Time (ns)
propagation delay is measured from the 50% point of the clk edge to the 50% point of the Q output
Sequential Logic
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Reduced Load MS ET FF
Clock load per register is important since it directly impacts the power dissipation of the clock network. Can reduce the clock load (at the cost of robustness) by making the circuit ratioed
clk
I1
!clk
I3
12 Transistors 4 clock loads
T
1
QM
I2
T
2
Q
I4 reverse conduction
!clk
clk
to switch the state of the master, T1 must be sized to overpower I2 to avoid reverse conduction, I4 must be weaker than I1
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Non-Ideal Clocks
Clk and !clk are never perfect inversions of one another

We must generate !clk and route both signals Variations can exist in the wires used to route the two clock
signals and load capacitances may vary
Non-ideal clocks create skew resulting in clock overlap

1-1 Overlap 0-0 Overlap
clk !clk
clk !clk
Ideal clocks
Non-Ideal clocks
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Example of Clock Skew Problems

clk Race D
P1
X A
I1 I2
!clk
P3
I3 I4
Q !Q
B
P2
P4
!clk
clk
Race condition direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap)
Undefined state both B and D are driving A when clk and !clk are both high
Dynamic storage when clk and !clk are both low (0-0 overlap)
Sequential Logic
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Pseudostatic Two-Phase ET FF
clk1 D
P1
X A
I1 I2
clk2
P3
I3 I4
Q !Q
B
P2
P4
clk2 master transparent slave hold
dynamic storage
clk1
clk1
clk2
tnon_overlap
Sequential Logic
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Two Phase Clock Generator

A clk1
clk
B clk2
clk
A B clk1 clk2
Sequential Logic
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Power PC Flipflop
clk !clk
1D
01
10
10
Q 01
!clk
clk
master transparent slave hold clk
16 Transistors 8 clock loads master hold slave transparent
!clk
Sequential Logic
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Overpowering The Feedback Loop

Clocked SR Latch Cross-coupled NANDs
S
M2 M4
Q !Q
clk S
M6 M1 M5 M3
M8
clk
R
M7
This is not used in datapaths any more, but is a basic building block for memory cell
Sequential Logic
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Ratioed CMOS Clocked SR Latch

off on
M2 M4
on off
Q 1 0
1 0 !Q off ->on
0 1 clk 0 S
M6
off ->on
M8
clk 0 1 R 1 8 Transistors 2 Clock loads*

* sized
on off
M5
M1
off on
M3
M7
off
on
No static power consumption, but a ratioed device where sizing is critical to ensure proper functionality
M7, M8 must overcome M4 to bring Q low, so must M5, M6
over M2
Sequential Logic
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Sizing Issues
2
(W/L)2 and 4 = 1.5m/0.25 m (W/L)1 and 3 = 0.5m/0.25 m
1.5
!Q (Volts)
so (W/L)5 and 6 > 3
0.5
0 2 2.5 3 3.5 4
(W/L)5 and 6
Output voltage depends on pull-down transistor width

Sequential Logic
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Transient Response
3
!Q
S
W=0.5 m W=0.6 m W=0.7 m
W=0.8 m W=1 m
!Q (Volts)
W=0.9 m
1.6 2
0 0 0.4 0.8 1.2
Time (ns)
Individual device ratio for M5 or M6 must be larger than approx. 6. Analysis results give 2.26 (instead of 3) since it doesnt take into account channel length modulation and DIBL (drain induced barrier loading).
Sequential Logic
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6 Transistor CMOS SR Latch

clk R clk S
Problems with noise margins and static power consumption due to threshold drop across pass transistors Once again, sizing is important - especially M5 and M6
clk R
M5
clk
M2 M4
Q !Q
M1 M3
M6
6 Transistors 2 Clock loads

Sequential Logic
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Review: Storage Mechanisms

Static (Positive Feedback)
CLK
Dynamic (charge-based)
CLK
Q
D
CLK
CLK
CLK
Useful when update is infrequent

Simpler, Faster, and Lower Power

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Sequential Logic
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Dynamic ET Flipflop
master
!clk
T1 I1
slave
clk QM
T2 I2
8 Transistors 4 Clock loads Q
C clk
master transparent slave hold
1
C !clk
2
clk !clk
tsu = tpd_tx thold = zero tc-q = 2 tpd_inv + tpd_tx

Sequential Logic
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Dynamic ET FF Race Conditions

!clk QM D
T1 I1 T2 I2
clk
C clk
1
C !clk
2
clk !clk
0-0 overlap race condition
toverlap0-0 < tT1 + tI1 + tT2

1-1 overlap race condition
toverlap1-1 < thold

Sequential Logic
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Dynamic Two-Phase ET FF
clk1 QM D
T1 I1 T2 I2
clk2
C !clk1
1
C !clk2
2
clk1 clk2
tnon_overlap
Sequential Logic
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Pseudostatic Dynamic Latch
Robustness considerations limit the use of dynamic FFs

Coupling between signal nets and internal storage nodes can
inject significant noise and destroy the FF state

Leakage currents cause state to leak away with time Internal dynamic nodes dont track fluctuations in VDD that
reduces noise margins
A simple fix is to make the circuit pseudostatic

clk
T1
!clk
Slight increase in delay (adds to the capacitive load) and power consumption, but it improves noise immunity significantly
Sequential Logic
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C2MOS (Clocked CMOS) ET Flipflop

Master
M2
Slave
M6
clk D !clk off
on
M4
QM C1
!clk on clk
off
M8
8 Transistors 4 Clock loads Q C2

Insensitive to clock overlap as long as the rise and fall times of the clock edges are sufficiently small
on
M3
off
M7
off
M1
on
M5
clk
!clk
Sequential Logic
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C2MOS FF 0-0 Overlap Case

M2 M6
0 D
M4
QM C1
M8
Q
M7 M5
M3 M1
C2
clk !clk
clk !clk
Sequential Logic
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Notes on C2MOS FF 0-0 Overlap Case
Does any new data sampled during the overlap window propagate to Q (race)?
New data is sampled on QM, but cannot propagate to Q since
M7 is off (slave is in hold).

Any new data sampled on the falling clock edge is not seen at Q
For clocking on the left: at the end of the overlap period !clk = 1 and both M7 and M8 turn off, putting the slave in the hold mode For the clocking on the right: at the end of the overlap period clk = 1 and both M3 and M4 turn off, putting the master in the hold mode (affects setup time as well) The result: the FF is slower (slower tc-q time)
Sequential Logic
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C2MOS FF 1-1 Overlap Case

M2 M4 M6
D 1
M3 M1
QM C1 1
M8
Q
M7 M5
C2
clk !clk
clk !clk 1-1 overlap constraint: toverlap1-1 < thold
Sequential Logic
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Notes on C2MOS FF 1-1 Overlap Case
New data is sampled on QM, but cannot propagate to Q since M8 is off (slave is in hold).
A bit more problematic than 0-0 overlap.

It must enforce a hold time on D, so that changing D which
reaches QM is not copied to Q when overlap time is over

first clocking condition.
By imposing a hold time on D - that D must be stable during
clock overlap - overcome this problem as well
However, possible race can occur if the rise/fall times of the clock are sufficiently slow.
Works correctly as long as the clock rise/fall times is smaller
than approximately five times the propagation delay of the flipflop.

Sequential Logic
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C2MOS Transient Response

3 2.5 2 1.5 1 0.5
QM(3) Q(3) Q(0.1) clk(0.1 ns) clk(3 ns)
0
-0.5 0 2 4 6 8
Time (nsec)
For slow clocks, potential for a race condition exists

Sequential Logic
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True Single Phase Clocked (TSPC) Latches

Negative Latch Positive Latch
Q In clk clk Q In clk clk
hold when clk = 1 transparent when clk = 0
transparent when clk = 1 hold when clk = 0
Uses only a single clock

No clock overlap (skew) to worry about ; reduced clock load
Sequential Logic
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Embedding Logic in TSPC Latch

PUN
Q In clk PDN clk clk A B A AND B
B
Q clk
Logic can be embedded into latch (or FF)

Reduce delay overhead associated with the latch
Sequential Logic
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Notes on Embedding Logic in TSPC Latch
Set-up time increased, but overall performance improved

The increase in the set-up time is typically smaller than the
delay of an AND gate.

For example, using minimum size devices set-up of AND
latch is 140 psec.

Using the conventional approach of AND gate followed by
latch has an effective set-up time of 600 psec.
Technique used extensively in the design of the EV4 DEC Alpha microprocessor and many other high performance processors.
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TSPC ET FF
Master Slave
clk
on off
clk
on QM off
on clk off
on clk off
master transparent slave hold clk
12 Transistors 4 Clock loads master hold slave transparent
Virtually all constraints removed - no clocks to overlap, no race

Sequential Logic
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Notes on TSPC ET FF
Warning! - similar to C2MOS, TSPC flipflops malfunction when the slope of the clock is not sufficiently steep.
Slow clock cause both the NMOS and PMOS
clocked transistors to be ON simultaneously, resulting in undefined values of the states and race conditions.
Clock slopes thus must be carefully engineered. If
necessary, local buffers must be introduced to ensure the quality of the clock signal
Sequential Logic
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Simplified TSPC ET FF
I1
M3
I2 clk off
I3
on M6 M9 Y1D clk on X !D clk off M2 off M5 on M8 clk off M1 M4 M7 on
Q D
I1 sample (transparent) I2 precharged I3 hold
9 Transistors* 4 Clock loads

*(11 if Q is needed)
clk
I1 hold I2 evaluate I3 sample (transparent)

Sequential Logic
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Notes on TSPC ET FF
On the positive edge of the clock, note that the node X transitions to a low if D is high. Therefore, the input must be kept stable until the value on node X before the rising edge of the clock propagates to Y
Hold time of the register (less than 1 inverter delay since it
takes 1 inverter delay for the input to affect node X).
Propagation delay is essentially three inverters since the value on node X must propagate to output Q Set-up time is the time for node X to be valid one inverter delay
Sequential Logic
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Sizing Issues in Simplified TSPC ET FF

3
clk !Qorig
!Qmod
Transistor sizing
Original width M4, M5 = 0.5m M7, M8 = 2m
Qmod Qorig
0 0 0.2 0.4 0.6 0.8 1
Time (nsec)
Modified width M4, M5 = 1m M7, M8 = 1m
Sizing is critical with improper sizing glitches may occur due to race condition when the clock transitions from low to high
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Split-Output TSPC Latches

Positive Latch Negative Latch
Q In clk A In clk
A Q
transparent when clk = 1 hold when clk = 0 When In = 0, A = VDD - VTn

hold when clk = 1 transparent when clk = 0 When In = 1, A = | VTp |

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Sequential Logic
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Split-Output TSPC ET FF
8 Transistors* 2 Clock loads
*(10 if Q is needed)
clk
A
clk
QM Q
Which edge-triggered?
Downside is not all node voltages in the latch experience full logic swing due to threshold drop.
E.g., for positive latch when D=0 and clk=1, A=Vdd-Vth (Also
limits the amount of Vdd scaling possible with this latch).

Sequential Logic
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Pulse-Triggered Flipflops
Another approach to design an edge-triggered flipflop is to use pulse-triggered.

Master-Slave Flipflop
Pulse-Triggered Flipflop
L1
Data D Clk Clk Q
L2
D Clk Q Data Clk D
L
Q
Clk
Sequential Logic
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Pulsed FF (AMD-K6)
Pulse registers - a short pulse (glitch clock) is generated locally from the rising (or falling) edge of the system clock and is used as the clock input to the flipflop
OFF 0/Vdd ON/OFF
clk
ON P1 X Vdd
P3
1/0
M3OFF
ON
M6OFF
ON
D
1 1
1/0 0 1 0
M2ON/
OFF
P2
M5
M1ON
ON OFF
!clkd
M4
Sequential Logic
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Notes on Pulsed FF
Race conditions are avoided by keeping the transparent mode time very short (during the pulse only)
Reduce clock load but substantially increase complexity in verification

The transparency period determines the hold time.
The window must be wide enough for the input data to
propagate to Q.
The set-up time can be NEGATIVE (if the transparency window is longer than the delay from input to output).
This is attractive, as data can arrive at the register even after
the clock goes high, meaning that time can be borrowed from the previous cycle.
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Sense Amp FF (StrongArm SA100)
Sense amplifier is a circuit that accept small swing input signals and amplify them to full rail-to-rail signals
0 1
D
M2
1 M5
M9 M7
!S Q
M1 1 M6 1 M8 M10 0 1
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M4
!R
M3 0
!Q
clk
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Notes on Sensed Amp FF
The key is transistor M4 (in the middle of Sensed amp); it delays signals that pass through to the other side of its terminal, making the change on the other side slower
When D = 1, Y changes after X due to the delay of M4. By the
time M6 reacts to the change at its terminal, it is already turned off by the terminal voltage at M4 (a 0). Thus, M6 holds a 1.
M4 also provides DC-leakage path to ground for either node X or Y in case that the inputs change their value after the positive edge of CLK arrives.
Advantages are reduced clock load and that it can be used as a receiver for reduced swing differential buses
Where does the differential signal enter?
Sequential Logic
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Flipflop Comparison Chart

Name Mux PowerPC Type
Static Static
#clk ld
8 (clk-!clk) 8 (clk-!clk)
#tr
20 16
tset-up
3tpinv+tptx
thold
0
tpFF
tpinv+tptx
2-phase
T-gate C2MOS
Ps-Static
Dynamic Dynamic
8 (clk1-clk2)
4 (clk-!clk) 4 (clk-!clk)
16
8 8 tptx to1-1 2tpinv+tptx
TSPC
S-O TSPC AMD K6
Dynamic
Dynamic Dynamic SenseAmp
4 (clk)
2 (clk) 5 (clk) 3 (clk)
11
10 19 20
tpinv
tpinv
3tpinv
SA 100
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Choosing a Clocking Strategy
Choosing the right clocking scheme affects the functionality, speed, and power of a circuit
Two-phase designs
+ robust and conceptually simple - need to generate and route two clock signals - have to design to accommodate possible skew between the
two clock signals
Single phase designs

+ only need to generate and route one clock signal + supported by most automated design methodologies + dont have to worry about skew between the two clocks - have to have guaranteed slopes on the clock edges
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Non-Bistable Sequential Circuits
Previously, we have defined a circuit having two stable states a bi-stable circuit Other regenerative circuits, which are nonbistable:
Monostable
Only one stable state -> Pulse generators, One-shot circuits
Astable
No stable states -> Oscillator, On-chip clock generator
Schmitt Trigger
A special regenerative circuit exhibiting hysteresis in VTC.
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Schmitt Trigger
Non-Bistable Sequential Circuits
Vou t
In Out
V OH
2 important properties
Hysteresis Fast Transition Time
V OL
at the output
VM
Sequential Logic
VM+
Vi n
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Noise Suppression using Schmitt Trigger
VIN
VM+
VOUT
VM-
t0
t0 + t p
Example: Switch Debouncer

Sequential Logic
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CMOS Schmitt Trigger

VDD
Moves switching threshold of the first inverter
M2
M4
VIN
M1
X
M3
VOUT
Low-to-High reff = kM1/(kM2 + kM4) High-to-Low reff = (kM1 + kM3)/kM2
Adapting the ratio between PMOS and NMOS, depending upon the direction of the transition results in a shift in switching threshold
Sequential Logic
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Schmitt Trigger Simulated VTC

M1 = 1 m/0.25 m, M2 = 3 m/0.25 m, M3 = 0.5 m/0.25 m M4 = 1.5 m/0.25 m
2.5 2.0 2.5 2.0
M4 = k x 0.5 m/0.25 m
Vout(V)
1.0 0.5 0.0 0.0
Vout(V)
1.5 VM2
VM1
1.5 1.0 0.5 0.0 0.0
k=1 k=3 k=2 k=4 0.5 1.0 1.5 Vin (V) 2.0 2.5
0.5
1.0 1.5 Vin (V)
2.0
2.5
Voltage Transfer Characteristics with hysteresis

Effect of varying the ratio of the PMOS device M4

72
Sequential Logic
B.Supmonchai
CMOS Schmitt Trigger (2)

M4 M6 M3
How does the gate operate?
VIN
M2
M5
VOUT
X
M1
Sketch VTC and find expression for VM- and VM+

Sequential Logic
73
B.Supmonchai
Review: Ring Oscillator

tp
Period: T = 2 x tp x N
Different Clock Duty-Cycles and phases can be derived using simple logic operations
Sequential Logic
74
B.Supmonchai
Voltage Controller Oscillator (VCO)
Oscillation frequency of a VCO is a function (typically nonlinear) of a control voltage

VD D
M6
VDD
M4
Schmitt Trigger restores signal slopes
M2
In
M1
Iref Vcontr
M3 M5
Iref
Current starved inverter
Delay of6a current starved inverter depends on the current limit available to discharge the load capacitance of the gate
(nsec)
Sequential Logic
75
Vcontr
M3 M5
Current starv
B.Supmonchai
Current-Starved Inverter Simulation
4 2
0.0 0.5
The device is in the subthreshold region when Vctrl is smaller than VT, resulting in large variations of tp as the drive current is exponentially dependent on the propagati drive voltage
Delay sensitive to
t pH L (nsec) tpHL (nsec)
V Vctrl (V) co ntr (V)
1.5
2.5
of control
76
noise and variation in Vctrl
Sequential Logic
B.Supmonchai
Differential Delay Element and VCO

- Vo2
in1
Vo1
+
in2
+
Vctrl
v1 v2
v3 v4
delay cell
two stage VCO
- Inverting Inputs/Outputs
Oscillator with even number + Non-Inverting Inputs/Outputs of stages can be implemented
Differential-type VCO has better immunity to common mode noise (e.g., supply noise) but consume more power
Sequential Logic
77
B.Supmonchai
2-Stage VCO Simulation

3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 0.5 0.5 1.5 time (ns) 2.5 3.5
V1 V2
V3
V4
The In-Phase and Quadrature Phase are produced simultaneously

Sequential Logic
78

Ch7 Sequential

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Ch7 Sequential

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Chapter 7

August 20, 2004; Revised - July 4, 2005

Goals of This Chapter

Implementation techniques for

Static versus Dynamic Realization

2102-545 Digital ICs

Storage Mechanisms Positive Feedback STATIC

Static vs Dynamic Storage

connection between the output and the input

require periodic refresh

Latches versus Flipflops

Latches (with Clock)

high (or low) - transparent mode

when clock is low (or high) - hold mode

Review: The Regenerative Property

Review: Bistable Circuits

2102-545 Digital ICs

Review: Clocked D Latch

D Q clock transparent mode

clock hold mode

In our course All latches mean clocked latches

Latches versus Flipflops II

Latch stores data when clock is low (high)

Flipflop stores data when clock rises (falls)

Positive and Negative Latches

Negative Latch Out In

clock tsu In thold

2102-545 Digital ICs

System Timing Constraints

tcd: contamination delay = minimum delay

tcdreg + tcdlogic thold

T tc-q + tplogic + tsu

Notes on System Timing Constraints

2102-545 Digital ICs

Building A (Static) Latch

Cutting the feedback loop (Mux-based latch)

MUX Based Latches

Change the stored value by cutting the feedback loop

TG MUX Based Latch Implementation

feedback (hold mode)

PT MUX Based Latch Implementation

feedback (hold mode)

Latch Race Problem

clk T tc-q + tplogic + tsu Thigh tc-q + tcdlogic

Which value of B is stored?

Two-sided clock constraint

Master Slave Based ET Flipflop

20 Transistors* 8 clock loads

master transparent slave hold clk !clk

master hold slave transparent

Propagation delay - time for QM to reach Q

Hold time - time D must be stable after rising edge of clk

2102-545 Digital ICs

Notes on MS ET Timing Properties

that QM samples the value reliably?

Propagation delay time

after clk goes high are not seen, so hold time is 0

Set-up Time Simulation

-0.5 0 0.2 0.4 0.6 0.8 1

Set-up Time Simulation II

Propagation Delay Simulation

tc-q (LH) = 160 psec

tc-q (HL) = 180 psec

12 Transistors 4 clock loads