library ieee; use ieee.std_logic_1164.

all; entity FSM is port( a_in : in std_logic; reset,clk :in std_logic; b_out :out std_logic ); architecture my_FSM of FSM is type my_state is (s0 ,s1 ,s2); signal present_state, next_state : my_state; begin state_reg:process(clk,reset) begin if (reset='1') then present_state<=s0; elsif(clk'event and clk='1') then present_state<=next_state; end if; end process state_reg; next_state :process(present_state,a_in) begin case present_state is when s0 => if (a_in = '1') then next_state<= s1; else next_state <= s0; end if; when s1 => if (a_in='0') then next_state <=s2; else next_state <= s1; end if; when s2 => if (a_in ='1') then next_state <= s1 else next_state <=s0; end if; end process next_state; out_logic: process(present_state,a_in)

begin case present_state is when s0 => b_out <='0'; when s1 => if (a_in ='1') then b_out <='0'; else b_out <='1'; end if; when s2 => b_out <= '0'; end process out_logic; end my_FSM;