library ieee; use ieee.std_logic_1164.

all; entity d_ff is port ( d ,r,s :in std_logic; clk: in std_logic; q: buffer std_logic ); end d_ff; architecture my_d_ff of d_ff is begin process(d,s,r,clk) begin if (clk'event and clk='1') then if (s='0') then q<='1'; elsif (r='0') then q<='0'; else q<=d; end if; end if; end process; end my_d_ff;