A Novel Filter-Bank Multicarrier Scheme to Mitigate the Intrinsic Interference-Application to MIMO Systems

Abstract
Filter-bank multicarrier (FBMC) transmission system was proposed as an alternative approach to orthogonal frequency division multiplexing (OFDM) system since it has a higher spectral efficiency. One of the characteristics of FBMC is that the demodulated transmitted symbols are accompanied by interference terms caused by the neighboring transmitted data in time-frequency domain. The presence of this interference is an issue for some multiple-input multiple-output (MIMO) schemes and until today their combination with FBMC remains an open problem. We can cite, among these techniques, the Alamouti scheme and the maximum likelihood detection (MLD) with spatial multiplexing (SM). In this paper, we shall propose a new FBMC scheme and transmission strategy in order to avoid this interference term. This proposed scheme (called FFTFBMC) transforms the FBMC system into an equivalent system formulated as OFDM regardless of some residual interference. Thus, any OFDM transmission technique can be performed straightforwardly to the proposed FBMC scheme with a corresponding complexity growth compared to the classical FBMC. First, we will develop the FFT-FBMC in the case of singleinput single-output (SISO) configuration. Then, we extend its application to SM-MIMO configuration with MLD and Alamouti coding scheme. Simulation results show that FFT-FBMC can almost reach the OFDM performance, but it remains slightly outperformed by OFDM.

Aim
To design and develop a Novel Filter-Bank Multicarrier Scheme

Objective
The objectives of this works are, 1. Design of a Novel Filter-Bank Multicarrier Scheme using VHDL. 2. Functional verification of the above design 3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.