A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX

Abstract

A wideband digital RF receiver front-end employing a discrete-time (DT) filter is presented for application to m-WiMAX (WiBro). By employing a sampling mixer and a DT filter, the receiver operates in the charge domain. In addition to the flexibility of the DT filter, the new non-decimation finite impulse response (NDF) filter can be cascaded to a conventional finite impulse response (FIR) filter without the decimation effect. Thus, we can easily increase the order of the function-type filtering response and the signal processing bandwidth. The FIR filter is also modified to reduce the noise and the number of required clock signal. Because of the new filter configuration, clock signals can be shared by the FIR filter and NDF filter and the clock generator circuit can be simplified. The designed receiver front-end is implemented using Spartan-3 XC3S400PQ208 field-programmable gate array from Xilinx, Inc.

Aim
To design Wideband Digital RF Receiver Front-End using FPGA

Objective
The objectives of this works are, 1. Design of Wideband Digital RF Receiver Front-End using VHDL 2. Functional verification of Wideband Digital RF Receiver Front-End 3. Result analysis in terms of a. Area b. Power

c. Speed Tools to be used:

For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.