An Optimization-Based Parallel Particle Filter for Multitarget Tracking

Abstract
Particle filters are used in state estimation applications because of their capability to solve nonlinear and non-Gaussian problems effectively. However, they have high computational requirements, especially in the case of multitarget tracking, where data association is the bottleneck. In order to perform data association and estimation together, an augmented state vector, whose dimensions depend on the number of targets, is typically used in particle filters. With data association, the computational load increases exponentially as the number of targets increases. In this case, parallelization is a possibility for achieving real-time feasibility in large-scale multitarget tracking applications. In the work presented here, an optimization-based scheduling algorithm, that is suitable for parallel implementation of particle filter, is presented. This proposed scheduling algorithm minimizes the total computation time for the bus-connected heterogeneous primary-secondary architecture. Further, this scheduler is capable of selecting the optimal number of processors from a large pool of secondary processors and mapping the particles among the selected ones. A new distributed resampling algorithm suitable for parallel computing is also proposed. Furthermore, a less communication-intensive parallel implementation of the particle filter without compromising tracking accuracy using an efficient load balancing technique, in which optimal particle migration among secondary processors is ensured, is presented.

Aim
To design Parallel Particle Filter using FPGA

Objective
The objectives of this works are, 1. Design of Parallel Particle Filter using VHDL 2. Functional verification of Parallel Particle Filter 3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.