Fixed-Point Implementation of Cascaded ForwardBackward Adaptive Predictors

Abstract
Adaptive least mean square (LMS) predictors with independently low-order cascaded structures, such as the cascaded forward LMS (CFLMS) and cascaded forwardbackward LMS (CFBLMS), have proven effective in combating the misadjustment and eigenvalue spread effects of linear predictors. Further developing this cascade structure, we study the fixed-point implementation of CFBLMS with applications to speech signals. Moreover, two groups of predictors with a total of six cases are compared. Group 1 employs the transversal structure for LMS, CFLMS, and CFBLMS algorithms. Group 2 employs the lattice structure for LMS, CFLMS, and CFBLMS algorithms. Experimental results show that, in group 1, the performance degradation of CFBLMS and CFLMS predictors becomes significant when the number of bits is reduced to 8, while that of the LMS predictor becomes significant when the number of bits is reduced to 9. On the other hand, in group 2, the performance degradation of CFBLMS and CFLMS predictors becomes significant when the number of bits is reduced to 5, while that of the LMS predictor becomes significant when the number of bits is reduced to 6. In both groups, the performances of CFBLMS and CFLMS are significantly superior to that of LMS, and CFBLMS is superior to CFLMS, in terms of the rate of convergence, misadjustment, and meansquare error (MSE).

Aim
To Design and Implement Fixed-Point Cascaded ForwardBackward Adaptive Predictors

Objective
The objectives of this works are, 1. Design and Implementation of Fixed-Point Cascaded ForwardBackward Adaptive Predictors using VHDL. 2. Functional verification of the above design 3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.