TRNG I HC BCH KHOA H NI KHOA IN T - VIN THNG s: 1 K duyt Tng s trang: 1

THI MN: IN T S Ln thi: 1 Ngy thi: 25/12/2009 Thi gian lm bi: 90 pht
(Khng s dng ti liu. Np thi cng vi bi lm)

Trng nhm Mn hc:

Trng B mn:

Cu 1 (2 im) a. Thit k mc cng (gate level design) mt mch s gm c u vo l mt s nh phn 3 bt v u ra l s nh phn biu din s bt 1 c trong s nh phn u vo. b. Thc hin mch thit k cu a ch s dng cc b MUX 4-1 v cng NOT. Cu 2 (2 im) Mt mch dy gm 2 Flip-flop JK, 2 u vo X v Y v mt u ra Z. Cho cc phng trnh u vo ca cc Flip-flop v phng trnh u ra Z nh sau: Z = Q1 XY + Q2 X Y K 1 = Q2 XY J 1 = Q2 X + Q2 Y J 2 = Q1 X K 2 = Q1 + XY a. V s mch in b. Xc nh bng chuyn trng thi v s chuyn trng thi ca mch Cu 3 (2 im) a. M t DFF vi 1 tn hiu reset ng b tch cc mc thp v 1 tn hiu set ng b tch cc mc thp dng VHDL b. M t 1 thanh ghi 4 bit s dng DFF m t cu a bng VHDL (gi : s dng cu trc khai bo component v cu trc port map ca VHDL) Cu 4 (4 im) Thit k FSMD thc hin thut ton tnh tng ca 10 s x ln hn 5 nh sau: cnt=0; sum=0; Repeat input x if (x > 5) then cnt=cnt + 1; sum=sum + x; end if; Until cnt=10; } output sum; Ch : 1. x v sum l cc s c gi tr cc i l 255. Cc lnh vit trn cng 1 hng c thc hin song song. 2. Ch r cc thanh ghi trong datapath l bao nhiu bit. 3. Biu din controller di dng FSM loi Moore v dng DFF thc hin. Cho bit bng trng thi v bng kch ca JKFF nh sau: J 0 0 1 1 K 0 1 0 1 Q (next) Q 0 1 Q Q Q(next) 0 0 0 1 1 0 1 1 Chc cc em sinh vin lm bi tt! 1 J 0 1 x x K x x 1 0