library ieee; use ieee.std_logic_1164.

all; entity dff is port(d :in std_logic; clk,en:in std_logic; q :out std_logic ); end dff; architecture my_gated_dff of dff is signal gated_clk :std_logic; begin process(clk,en) gated_clk<=clk when en='1' else '1'; begin if (gated_clk'event and gated_clk='1') then q<=d; end if; end process; end my_gated_dff;