Copyright (c) IRF Group

Nghin cu kho st b vi iu 8 bit PIC16F877

1. Gii thiu b vi iu khin 8 bt Ngy nay, cc b vi iu khin ang c ng dng ngy cng rng ri trong cc lnh vc k thut v i sng x hi, c bit l trong k thut t ng ho v iu khin t xa. Gi y vi nhu cu chuyn dng ho, ti u (thi gian, khng gian, gi thnh), bo mt, tnh ch ng trong cng vic... ngy cng i hi kht khe. Vic a ra cng ngh mi trong lnh vc ch to mch in t p ng nhng yu cu trn l hon ton cp thit mang tnh thc t cao. 1.1. Khi nim v b vi iu khin hiu khi nim v b vi iu khin, ta c th lm php so snh n vi b vi x l cng dng chung nh sau: Ta bit rng, cc b vi x l cng dng chung nh h Intel x86 (8086, 80286, 80386, 80486 v Pentium) hoc h Motorola 680x0(6800, 68010, 68020, 68030, 68040 vv...) khng c RAM, ROM v khng c cc cng ra vo trn chip... Vi l do m chng c gi l cc b vi x l cng dng chung. Mt nh thit k h thng s dng mt b vi x l cng dng chung chng hn nh Pentium hay 68040 s phi b xung thm RAM, ROM, cc cng vo ra v cc b nh thi ngoi lm cho chng hot ng c. Mc d vic b xung cc RAM, ROM, cc cng vo ra s lm cho h thng cng knh ln nhng n li c u im khi s dng cc b vi x l ny l rt linh hot. Chng hn nh ngi thit k c th quyt nh v s lng RAM, ROM, v cc cng vo ra cn thit sao cho ph hp vi kh nng, mc ch s dng ca h thng. iu ny khng th c i vi cc b vi iu khin. Bi v, mt b vi iu khin c mt CPU (mt b vi x l) cng vi mt s lng RAM, ROM, cc cng vo ra v mt b nh thi trn cng mt chp. Hay ni cch khc l b vi x l, RAM, ROM, cc cng vo ra v mt b nh thi cng c nhng trn mt chip. Do vy ngi thit k khng th b xung thm b nh ngoi, s cc cng vo ra hoc b nh thi cho n. Vi s lng RAM, ROM v s cc cng vo ra c nh nh vy l mt mt hn ch (km linh hot) xong n li tht s l tng i vi nhng ng dng mang tnh chuyn bit, ti u v gi thnh, ti u v khng gian... Hin nay trn th trung c cc b vi iu khin 8 bt chnh l. 6811 ca Motorola, 8051 ca Intel, Z8 ca Xilog v Pic16x ca Microchip Technology. Mi loi trn y u c mt tp lnh v thanh ghi ring duy nht, nn chng u khng tng thch ln nhau. Cng c nhng b vi iu khin 16 bt v 32 bt c sn xut ra bi cc hng sn xut chp khc nhau. 1.2. Nhng yu cu la chn mt b vi iu khin l:

Copyright (c) IRF Group p ng nhu cu tnh ton ca bi ton mt cch hiu qu v mt gi thnh v y chc nng c th nhn thy c, (kh d). C sn cc cng c pht trin phn mm chng hn nh cc trnh bin dch trnh hp ng v g ri. Ngun cc b vi iu khin c sn nhiu v tin cy. 1.3. Cc tiu chun la chn mt b vi iu khin: Tiu chun u tin v trc ht trong la chn mt b vi iu khin l n phi p ng nhu cu bi ton v mt cng sut tnh ton, gi thnh v hiu qu. Trong khi phn tch cc nhu cu ca mt d n da trn b vi iu khin, chng ta trc ht phi bit l b vi iu khin no l 8 bt, 16 bt hay 32 bt c th p ng tt nht nhu cu tnh ton ca bi ton mt cch hiu qu nht. Nhng tiu chun c a ra cn nhc l: Tc : Tc ln nht m b vi iu khin h tr l bao nhiu. Kiu ng v: l kiu 40 chn DIP hay QFP hay l kiu ng v khc. y l iu quan trng i vi yu cu v khng gian, kiu lp rp v to mu th cho sn phm cui cng. Cng sut tiu th: iu ny c bit kht khe i vi nhng sn phm dng pin, c quy. Dung lng b nh RAM v ROM trn chp. S chn vo ra, b nh thi, s ngt trn chp. Kh nng d dng nng cp cho hiu sut cao hoc gim cng sut tiu th. Gi thnh cho mt n v: iu ny quan trng quyt nh gi thnh cui cng ca sn phm m mt b vi iu khin c s dng. 2. B Vi iu khin 8 bit PIC16F877 2.1. c tnh ni bt ca b vi x l. + S dng cng ngh tch hp cao RISC CPU. + Ngi s dng c th lp trnh vi 35 cu lnh n gin. + Tt c cc cu lnh thc hin trong mt chu k lnh ngoi tr mt s cu lnh r nhnh thc hin trong 2 chu k lnh. + Tc hot ng l: - Xung ng h vo l DC- 20MHz - Chu k lnh thc hin trong 200ns + B nh chng trnh Flash 8Kx14 words + B nh Ram 368x8 bytes + B nh EFPROM 256x 8 bytes Kh nng ca b vi x l ny + Kh nng ngt ( ln ti 14 ngun ngt trong v ngt ngoi ) + Ngn nh Stack c phn chia lm 8 mc + Truy cp b nh bng a ch trc tip hoc gin tip. + Ngun khi ng li (POR) + B to xung thi gian (PWRT) v b to dao ng (OST)

Copyright (c) IRF Group + B m xung thi gian (WDT) vi ngun dao ng trn chp (ngun dao ng RC ) hot ng ng tin cy. + C m chng trnh bo v. + Phng thc ct gi SLEEP + C bng la chn dao ng. + Cng ngh CMOS FLASH /EEPROM ngun mc thp ,tc cao. + Thit k hon ton tnh . + Mch chng trnh ni tip c 2 chn. + X l c /ghi ti b nh chng trnh . + Di in th hot ng rng : 2.0V n 5.5V + Ngun s dng hin ti 25 mA + Dy nhit cng nghip v thun li . + Cng sut tiu th thp: < 0.6mA vi 5V, 4MHz 20 A vi ngun 3V, 32 kHz < 1 A ngun d phng. Cc c tnh ni bt ca thit b ngoi vi trn chip + Timer0: 8 bt ca b nh thi, b m vi h s t l trc + Timer1: 16 bt ca b nh thi, b m vi h s t l trc, c kh nng tng trong khi ch Sleep qua xung ng h c cung cp bn ngoi. + Timer 2: 8 bt ca b nh thi, b m vi 8 bt ca h s t l trc, h s t l sau + C 2 ch bt gi, so snh, iu ch rng xung(PWM). + Ch bt gi vi 16 bt, vi tc 12.5 ns, ch so snh vi 16 bt, tc gii quyt cc i l 200 ns, ch iu ch rng xung vi 10 bt. + B chuyn i tn hiu s sang tng t vi 10 bt . + Cng truyn thng ni tip SSP vi SPI phng thc ch v I2C(ch/ph) + B truyn nhn thng tin ng b, d b(USART/SCL) c kh nng pht hin 9 bt a ch. + Cng ph song song (PSP) vi 8 bt m rng, vi RD, WR v CS iu khin.

Copyright (c) IRF Group S cc chn PIC16F87X.

Copyright (c) IRF Group S khi b vi iu khin PIC16F87X

2.2. So snh vi b vi iu khin 8051 *B vi iu khin 8051 l b VK u tin thuc h VK x51 c sn xut bi cng ty Intel, Siemens, Advanced Micro Devices, Fujitsu, Philips. Cc c im chung ca b VK ny: 4KB ROM 128 B RAM 4 cng I/O 8 bit 2 Timer 16 bit C kh nng qun l c 64 KB b nh m chng trnh ngoi (ROM ngoi). C kh nng qun l c 64 KB b nh d liu ngoi (RAM ngoi) C b x l logic ring (thao tc trn cc bit) C th thao tc trc tip c 210 bit (cc bit ny c a ch ho) C 5 ngt Dng ngun dao ng ngoi

Copyright (c) IRF Group Dng in p 5V cho chip hot ng *Cng P0: C dng cc mng h v c 8 chn (8 bit) l cng vo/ra hoc l cng chuyn d liu v a ch. *Cng P1: L cng vo/ra c 8 chn (8 bit). *Cng P2: C 8 chn (8 bit) l cng vo/ra hoc l cng chuyn d liu v a ch. *Cng P3: C 8 chn, cng ny c th l cng vo/ra 8 bit hay cn c cc chc nng quan trng khc nh phc v cho ngt, cc b nh thi, vic truyn nhn d liu truyn thng ni tip, c v ghi cc b nh ngoi S khi ca VK 8051:
Timer 0 Timer 1 Serial Ports T0 T1

Int1 Int 0

Interupt control

RAM128 bytes Registers

ROM 4K

Timer 0 Timer 1

CPU
Oscilator Bus I / O Ports

Serial port

P0 P2 GND

P1 P3

TxD

RxD

Nh vy c th thy c im u tin m PIC16F877 em li v ni bt so vi VK 8051 l dng PIC16F877 nhng c tnh k thut hn hn so vi b VK 8051 th hin nhng im sau: VK8051 VK PIC16F877 c tnh S lng c tnh S lng ROM trn chp 4K byte ROM trn chp 8K RAM 128 byte RAM 368 byte B nh thi 2 B nh thi 3 Cc chn vo ra 32 Cc chn vo ra 40 Cng ni tip 1 Cng ni tip 2 Ngun ngt 6 Ngun ngt 14 Ngoi nhng c tnh trn th b vi iu khin PIC16F877 cn c mt c im hn hn so vi 8051 l c 10 bt chuyn i A/D trn chp iu ny s gip chng ta khng phi mt mt b chuyn i (s dn n kt ni dy tr nn phc tp). Mt c im na l b vi iu khin PIC16F877 c b to dao ng ch trn chp iu ny s trnh c nhng sai s khng cn thit trong vic to

Copyright (c) IRF Group xung dao ng, vi iu khin PIC16F877 c kh nng t Reset bng b WDT, v c thm 256 byte EEPROM.

2.3. S t chc b nh Pic16F877.

Pic16F877 c 3 khi b nh. B nh chng trnh PLASH, b nh d liu RAM, b nh EEPROM. 2.3.1. S t chc b nh chng trnh FLASH v Stack nh. Vi iu khin PIC16F877 c mt b m chng trnh 13 bit v c 8Kx14 t m ca b nh chng trnh FLASH, c chia thnh 4 trang mi trang 2Kx14 t m. Khi Reset a ch bt u thc hin chy l 0000h, Vector ngt bt u 0004h. Stack c 8 mc dng lu a(PC) ch lnh thc hin tip theo sau lnh CALL v khi xy ra ngt. Bn b nh chng trnh v cc ngn xp.

2.3.2. S t chc b nh d liu RAM RAM l b nh c th c v ghi, n khng lu d liu khi mt in, b nh RAM ca PIC16F877 c 4 bank, mi bank c di a ch 0-7FH(128byte) trn cc bank nhng thanh ghi a mc ch, n hot ng nh mt RAM

Copyright (c) IRF Group tnh.(General purpose register), v nhng thanh ghi chc nng c bit(Special function registers) vng a ch thp. Bt RP1(Status <6>) v bit RP0(Status <5>) dng la chn bank lm vic. RP1:RP0 Bank 00 0 01 1 10 2 11 3 Hnh nh cc bank nh sau:

Cc thanh ghi a mc ch: (General Purpose Register), cc thanh ghi ny c truy cp bng c hai cch trc tip hoc gin tip qua thanh ghi FSR,tng cng c 368 byte. Cc thanh ghi chc nng c bit. Cc thanh ghi ny c dng bi CPU v cc khi ngoi vi iu khin s hot ng theo yu cu ca thit b.

Copyright (c) IRF Group Cc thanh ghi ny c th c phn loi vo hai b phn trung tm (CPU) v ngoi vi. Sau y l mt s thanh ghi c bit quan trng. * Cc thanh ghi trng thi STATUS: C 4 thanh ghi trng thi trn 4 dy, ti cc a ch 03h, 83h, 103h, 183h. Cc thanh ghi ny cho bit trng thi ca phn t lgic ton hc ALU, trng thi RESET, trng thi ca cc bit la chn dy thanh ghi cho b nh d liu. Thanh ghi trng thi c th l kt qu ca mt s lnh nh l vi mt s thanh ghi khc. Nu thanh ghi trng thi l kt qu bi mt lnh m tc ng n cc bit Z, DC, C th vic ghi vo cc bit ny l khng th. * Cc thanh ghi la chn OPTION_REG: C hai thanh ghi la chn ti cc a ch 81h v 181h, cc thanh ghi ny c th c hoc ghi, n cha ng nhiu bit iu khin khc nhau xc nh h s nh trc TMR0/h s nh sau WDT, ngt ngoi INT, TMR0, cc in p treo trn cng B * Cc thanh ghi INTCON: C 4 thanh ghi INTCON ti cc a ch 0Bh, 8Bh, 10Bh, 18Bh. Cc thanh ghi ny c th c v ghi, n cha ng nhiu s cho php v cc bit c cho vic trn thanh ghi TMR0, cc ngt thay i cng RB v chn cc ngt ngoI RB0/INT. * Thanh ghi PIE1: Ti a ch 8Ch, cha ng cc bit cho php ring l cho cc ngt ngoi vi. * Thanh ghi PIR1: Ti a ch 0Ch, cha ng cc bit c ring l cho cc ngt ngoi vi. * Thanh ghi PIE2: Ti a ch 8Dh, cha ng cc bit cho php ring l cho cc ngt ngoi vi CCP2, ngt xung t tuyn SSP v EEPROM ghi cc hot ng ngt . * Thanh ghi PIE2: Ti a ch 8Dh, cha ng cc c bit cho cc ngt ngoi vi CCP2, ngt xung t tuyn SSP v EEPROM ghi cc hot ng ngt . * Thanh ghi PCON (Power Control): Cha bit c cho php phn bit gia vic Reset h thng (POR) Reset MCLR ngoi vi Reset WDT. * PCL v PCLATH. Chng trnh m ch r a ch ca lnh tip theo c thc hin. PC c rng 13 bit, byte thp c gi l thanh ghi PCL, thanh ghi ny c th c hoc ghi. Byte cao c gi l thanh ghi PCH, n cha cc bit PC<12:8> v khng trc tip c hoc ghi m ton b s cp nhp ca n thng qua thanh ghi PCLATH. Khi reset 5 bit PCLATH<4:0> np ti PCH, khi thc hin cc lnh CALL, GOTO 11 bit Ofcode<10:0> v 2 bit PCLATH<4:3> to thnh 13 bit np vo PC. Do vy khi dng lnh CALL, GOTO ch n hai bit PCLATH<4:3> cng chnh l hai bit ch cc trang ca b nh chng trnh.

Hnh nh s np PCLATH ti PC

Copyright (c) IRF Group

2.3.3. Cc trang b nh chng trnh. PIC16F877 c 8Kx14 PLASH cc lnh CALL, GOTO ch cung cp 11 bit a ch cho php r nhnh c 2k<0->211-1>ca mt trang b nh chng trnh 2 bit cao c cung cp bi 2 bit 3,4 ca PCLATH<4:3> do vy tu vic thit lp cc bit 3,4 ca PCLATH trc khi lnh CALL, GOTO thc hin cho php r nhnh ti cc trang b nh khc nhau. Ch cc lnh RETURN, RETFIE khng lm thay i PCLATH V d t trang 0 gi chung trnh con trang 1 nh sau ORG 0000h Goto main main BSF PCLATH,3 BCF PCLATH,4 CALL SUB1 BCF PCLATH,3 BCF PCLATH,4 LOOP GOTO LOOP ORG 0X800H SUB1

Copyright (c) IRF Group RETURN END 2.3.4. Truy cp b nh RAM bng a ch trc tip, gin tip.

* V d c nh 0xE0 bng a ch trc tip BSF STATUS,RP0 ;chn bank 1 BCF STATUS,RP1 MOVF 0XE0,W ;copy nh 0xE0( bank 1) ti W BCF STATUS,RP0 ;chn bank0 BCF STATUS,RP1 MOVF 0X30,W ;copy nh 0x30( bank 0) ti W * Truy cp RAM bng a ch gin tip Thanh ghi FSR ch ra a ch(0->0XFF) nh cn truy cp, thanh ghi INDF cho ni dung nh truy cp, bit IRP thanh ghi STATUS<7> ch ra bank truy cp v d xo cc nh t a ch 0x20-0xFF MOVLW 0X1A MOVWF FSR BCF STATUS,IRP ;bank 0

Copyright (c) IRF Group LOOP INCF FSR, F CLRF INDF MOVF FSR, W XORLW 0XFF BTFSS STATUS, ZR GOTO LOOP 2.3.5. B nh d liu EEPROM v b nh chng trnh FLASH. Cc b nh ny c th c v ghi trong khi cc hot ng vn din ra bnh thng. B nh d liu khng trc tip sp xp d liu trn cc thanh ghi d liu cn trng. Thay v l nh cc a ch gin tip qua cc thanh ghi chc nng c bit. C 6 thanh ghi SFR dng c v ghi b nh chng trnh v b nh d liu EEPROM l cc thanh ghi: EECON1 EEDATH EECON2 EEADR EEDATA EEADRH B nh d liu EEPROM cho php c v ghi cc byte. Khi c tc ng ti khi b nh d liu. Thanh ghi EEDATA gi 8 bit d liu c/ghi v thanh ghi EEADR gi a ch v tr ca EEPROM c truy cp. Cc thanh ghi EEDATH v EEADRH khng c s dng truy cp d liu EEPROM. Cc thit b ny c ti 256 byte ca d liu EEPROM vi a ch t 00h ti FFh. B nh d liu EEPROM c xp vo loi cao cho cc chu trnh xo/ghi. Thi gian c iu khin bi mt b nh thi trn chip. Thi gian ghi s thay i cng vi in th v nhit . B nh chng trnh cho php c v ghi cc k t. Khi tc ng n khi chng trnh nh, cc thanh ghi EEDATH, EEDATA c dng 2 byte k t gi 14 bit d liu c/ghi v cc thanh ghi EEADRH, EEADR c dng hai bit t m vi 13 bit a ch ca v tr EEPROM c truy cp. Nhng thit b ny c th c ti 8K t m ca chng trnh EEPROM vi mt a ch gii hn t 0h ti 3FFh. * Thanh ghi EEADR. Thanh ghi a ch c th nh a ch ln nht l 256 Byte ca d liu EEPROM hoc ln nht l 8K k t ca chng trnh FLASH. Khi la chn gi tr mt a ch chng trnh, byte MS ca a ch s c ghi vo thanh ghi EEADRH v byte LS c ghi vo thanh ghi EEADR. Khi la chn mt gi tr a ch d liu, ch c byte LS ca a ch c ghi ti thanh ghi EEADR. * Cc thanh ghi EECON1 v EECON2. EECON1 l thanh ghi iu khn cho vic nhp d liu b nh. EECON2 khng phI l thanh ghi vt l. Khi c thanh ghi EECON2 s c ton b l 0. Thanh ghi EECON2 c s dng dnh ring cho vic ghi mt cch trnh t vo b nh.

Copyright (c) IRF Group Bit iu khin EEPGD xc nh nu vic nhp d liu s l nhp mt chng trnh hoc nhp mt b nh d liu. Khi xo, mt s hot ng tip theo s hot ng trn b nh d liu. Khi set, mt s hot ng tip theo s hot ng trn b nh chng trnh. Cc bit iu khin RD v WR kch hot cc hot ng c v ghi theo th t. Trong phn mm nhng bit ny khng th b xo, ch c set. Chng b xo trong phn cng khi m cc hot ng c hoc ghi hon thnh. Vic khng th xo bit WR trong phn mm ngn nga s kt thc bt ng hoc kt thc sm ca mt hot ng ghi. 2.3.6. c b nh d liu EEPROM. c mt v tr b nh d liu, ta phi ghi a ch vo thanh ghi EEADR, xo bit iu khin EEPGD (EECON1<7>) sau set bit iu khin RD (EECON1<0>). D liu vn tn ti trn nhiu lnh tip theo trn thanh ghi EEDATA, do n c th c c bi lnh tip theo. EEDATA s gi gi tr ny cho ti khi c hot ng c d liu khc hoc l ti khi c ghi. V d: c d liu EEPROM. BSF STATUS, RP1 ; BCF STATUS, RP0 ; Chn dy 2 MOVF ADDR, W ; a ch b nh d liu c MOVWF EEADR ; BSF STATUS, RP0 ; Dy 3 BCF EECON1, EEPGD ; Chuyn ti b nh d liu BSF EECON1, RD ; bt u hot ng c BCF STATUS, RP0 ; Dy 2 MOVF EEDATA, W ; W = EEDATA 2.3.7. Ghi vo b nh d liu EEPROM. ghi vo b nh EEPROM th u tin a ch phi c ghi vo thanh ghi EEADR v d liu ghi vo thanh ghi EEDATA, v trnh t c tin hnh nh v d sau: V d: Ghi d liu EEPROM. BSF STATUS, RP1 ; BSF STATUS, RP0 ; Dy 3 BTFSC EECON1, WR ; i cho GOTO $-1 ; vic ghi kt thc BCF STATUS, RP0 ; Dy 2 MOVF ADDR, W ; a ch MOVWF EEADR ; ghi vo EEADR MOVF VALUE, W ; d liu MOVWF EEDATA ; ghi vo EEDATA BSF STATUS, RP0 ; Dy 3 BCF EECON1, EEPGD ; Con tr ti b nh d liu

Copyright (c) IRF Group BSF EECON1, WREN BCF INTCON, GIE MOVLW 0x55 MOVWF EECON2 MOVLW 0xAA MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF ECON1,WREN ; Cho php ghi ch khi cc ngt khng cho php ; ; ghi 55h ti ; EECON2 ; ghi AAh ti ; EECON2 ; Bt u hot ng ghi ch khi cc ngt cho php ; Nu dng cc ngt otherwise discard ; khng th ghi

2.3.8. c chng trnh FLASH. c mt v tr b nh chng trnh c th c thc hin bi vic ghi 2 byte a ch vo cc thanh ghi EEADR v EEADRH, set bit iu khin EEPGD (EECON1<7>) v sau set bit iu khin RD (EECON1<0>). Ch khi bit iu khin c c set, vi x l s s dng chu trnh lnh th hai c d liu. D liu s c trong chu trnh th 3, trong thanh ghi EEDATA v EEDATH, do n c th c l hai byte trong cc lnh tip theo. D liu c th c a ra ngoi ca EEDATH:EEDATA bt u vi lnh th 3 sau lnh BSF EECON1, RD. V hai thanh ghi EEDATA v EEDATH s gi gi tr ny cho ti khi c hot ng c mt gi tr khc hoc c hot ng ghi. V d: BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVF ADDRL, W ; Write the MOVWF EEADR ; address bytes MOVF ADDRH,W ;for the desired MOVWF EEADRH ; address to read BSF STATUS, RP0 ; Bank 3 BSF EECON1, EEPGD ;Point to Program memory BSF EECON1, RD ;Start read operation NOP ;Required two NOPs NOP ; BCF STATUS, RP0 ;Bank 2 MOVF EEDATA, W ;DATAL = EEDATA MOVWF DATAL ; MOVF EEDATH,W ;DATAH = EEDATH MOVWF DATAH ; 2.3.9. Ghi ti FLASH. ghi mt v tr b nh chng trnh c th c thc hin bi vic ghi 2 byte a ch vo cc thanh ghi EEADR v EEADRH, ghi d liu 13 bit vo 2 thanh ghi EEDATA v EEDATH theo v d sau.

Copyright (c) IRF Group V d: BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVF ADDRL, W ; ghi a chi MOVWF EEADR ; MOVF ADDRH,W ; MOVWF EEADRH ; MOVF VALUEL,W ; ghi d liu MOVWF EEDATA MOVF VALUEH,W MOVWF EEDATH BSF STATUS, RP0 ; Bank 3 BSF EECON1, EEPGD ;Point to Program memory BSF EECON1, WREN ;enable write operation BCF INTCON,GIE ; cm ngt nu ngt cho php MOVLW 0x55 ; ghi 55h ti MOVWF EECON2 ; EECON2 MOVLW 0xAA ; ghi AAh ti MOVWF EECON2 ; EECON2 BSF EECON1,WR NOP NOP BCF EECON1, WREN ;disable write operation BSF INTCON,GIE ; ngt hot nu ngt cho php 2.4. Cng vo ra Mt s chn ca cc cng vo/ra c tch hp vi mt s hm c th thay i ph hp vi nhng thit b ngoi vi. Nhn chung khi tht b ngoi vi hot ng, cc chn c th khng s dng vi mc ch lm chn vo ra. 2.4.1. Cng A v thanh ghi TRISA Cng A l cng hai chiu vi rng ng truyn l 6 bit. iu khin vic truy xut d liu ngi ta dng thanh ghi TRISA . Nu t bt TRISA = 1 th lc ny cng A s tng ng c cc chn l chn vo .Nu xo bt TRISA = 0 th lc ny cng A s tng ng c cc chn l chn ra. Vic c cng A chnh l c trng thi ca cc chn, trong khi vic vit phi qua vic vit cc cht ca cng. Cc chn ca cng A ch yu c s dng vi mc ch chnh l nhn tn hiu tng t hoc lm cc chn vo ra. Ring chn RA4 c th a hp vi chn vo b Timer 0 v khi n tr thnh chn RA4/T0CKI. Chn ny nh mt u vo ca Schmitt Trigger v n m u ra. Cc chn khc ca cng A l chn vo vi b TTL. Vic iu khin cc chn ny thng qua vic t hay xo cc bt ca thanh ghi ADCON1. Thang ghi TRISA iu khin trc tip cc chn ca cng A,

Copyright (c) IRF Group khi s dng cc chn ny nhn tn hiu tng t vo ta phi chc chn rng cc bt ca thanh ghi TRISA c t ri S khi chn RA3:RA0 v chn RA5 v ca chn RA4/TOCKI ca cng A

2.4.2. Cng B v thanh ghi TRISB Cng B l cng hai chiu vi rng ng truyn l 8 bit.Tng ng vi n iu khin trc tip d liu ta s dng thanh ghi TRISB. Nu t bt TRISB = 1 th lc ny cc chn ca cng B c nh ngha l chn vo. Nu xo bt TRISB = 0 th lc ny cc chn ca cng B c nh ngha l chn ra. Ni dung ca cht ra c th chn trn mi chn. C 3 chn ca cng B c th a hp vi cc chng trnh vn hnh bng in p thp. l cc chn sau: RB3/PGM, RB6/PGC, RB7/PGD. S thay i hot ng ca nhng chn ny c miu t trong phn c tnh ni bt. Mi chn ca cng B c mt kh nng dng bn trong nhng yu. iu ny c trnh by bi vic xo bt RBPU (bt 7 ca thanh ghi OPTION_REG). Kh nng dng ny s t ng tt i khi cc chn ca cng c nh ngha l chn ra. Kh nng dng ny s t ng mt i khi ta RESET. Bn chn ca cng B, t RB7 n RB4 c c tnh l ngt khi thay i trng thi. Ch nhng chn c nh dng l nhng chn vo th ngt ny mi tn ti. Mt vi chn RB7:RB4 c nh dng nh chn ra no thi hnh ngt trn s thay i so snh. Chn vo RB7:RB4 c so snh vi gi tr c ca cht ln c cui cng ca cng B.

Copyright (c) IRF Group S ghp i khng khp chn ra ca RB7:RB4 bng lnh OR lm pht ra ngt vi c bt RBIF ca thanh ghi INTCON. Ngt ny c th khi ng thit b t trng thi SLEEP. S khi ca chn RB3 n RB0 , chn RB7 : RB4 ca Cng B

2.4.3. Cng C v thanh ghi TRISC Cng C l cng hai chiu vi rng ng truyn l 8 bit .Tng ng vi vic iu khin n l thanh ghi TRISC. Nu t bt TRISC = 1 th tng ng vi chn ca cng C l chn vo. Nu ta xo bt TRISC = 0 th tng ng vi n chn ca cng C l chn ra . t ni dung ca cht ra c th t trn chn chn. Cng C a hp vi vic vn hnh thit bi ngoi vi. Chn ca cng C thng qua b m Schmitt Trigger u vo. Khi ch I2C hot ng, th cc chn cng PORTC<4:3> c th c sp xp vi mc I2C thng hoc vi mc SMBUS bng cch s dng bit CKE (SSPSTAT<6>) l bt 6 ca thanh ghi SSPSTAT. Khi vn hnh cc thit b ngoi vi bng vic xc nh bt TRIS ca mi chn cng C. Mt s phn ph c th ghi ln bt TRISC lm cho chn ny tr thnh chn ra, trong khi th mt s phn ph khc li ghi ln bt TRIS lm cho chn ny tr thnh chn vo. T khi nhng bit TRIS ghi th trong vic tc ng trong cc thit b ngoi vi l c th, nhng lnh c-sa- ghi (BSF, BCF, XORWF) vi thanh ghi TRISC nh l ni gi ti s c trnh. Ngi s dng nn cp ti vic phn chia kt ni cc thit b ngoi vi cho vic set chnh xc cc bit TRIS. S khi chn RC <0 : 2 > RC< 5: 7 > v chn RC < 3: 4> cng C

Copyright (c) IRF Group

2.4.4. Cng D v thanh ghi TRISD Cng D c 8 bt c b m u vo Schmitt Trigger. Mi chn c sp xp ring l nh u vo hoc u ra. Cng D cng c th c sp xp nh l mt cng vi x l 8 bit (cng ph song song) bng vic t bt iu khin PSPMODE(TRISE<4>) v trong ch ny vng m u vo l TTL.

S khi cng D

Copyright (c) IRF Group

2.4.5. Cng E v thanh ghi TRISE Cng E c 3 chn l RE0/RD/AN5, RE1/WR/AN6, RE2/CS/AN7. Cc chn ny c th sp xp ring l l cc u vo hoc cc u ra, v cc chn c vng m u vo l cc mch Schmitt Trigger. Cng vo/ra E tr thnh u vo iu khin cho cng vi x l khi bit PSPMODE(TRISE<4>) c t. V trong ch ny phi chc chn rng cc bit TRISE<2:0> c t (cc chn c nh dng l cc u vo s), thanh ghi ADCON1 phi c nh dng cho vic s vo/ra v vng m u vo l TTL. Cc chn cng E cng c tch hp vi cc u vo tng t v trong trng hp ny cc chn s c l 0. Thanh ghi TRISE iu khin trc tip cc chn RE, ngay c khi chng c dng l cc u vo tng t.

S khi ca cng E :

Copyright (c) IRF Group

2.5. Cc B Timer ca chip: B vi iu khin PIC16F87X c 3 b Timer l:Timer0, Timer1, Timer2 2.5.1. B Timer 0 L b nh thi hoc b m c nhng u im ni bt sau: + 8 bit cho timer hoc b m + C kh nng c v vit + C th dng ng h bn trong hoc bn ngoi + C th chn cnh xung ca xung ng h + C h s chia cho xung u vo c th lp trnh li bng phn mm + Ngt trn Hot ng ca Timer 0: Timer 0 c th hot ng nh mt b nh thi hoc mt b m. Vic chn b nh thi hoc b m c th c xc lp bng vic xo hoc t bt TOCS ca thanh ghi OPTION_REG<5>. Nu dng h s chia xung u vo th xo bit PSA ca thanh ghi OPTION_REG<3>. Trong ch b nh thi c la chn bi vic xo bit T0CS (OPTION REG<5>), n s c tng gi tr sau mt chu k lnh nu khng chn h s chia xung u vo. V gi tr ca n c vit ti thanh ghi TMR0. Ch m c la chn bi vic set bit T0CS (OPTION REG<5>). Trong ch b m, n s c tng xung i xung nu xo bit T0SE

Copyright (c) IRF Group (OPTION_REG<4>) hoc xung i ln nu set bit T0SE. V gi tr ca n c vit ti thanh ghi TMR0. Khi dng xung clock bn ngoi cho b nh thi Timer0 v khng dng h s chia clock u vo Timer0 th phi p ng cc iu kin cn thit c th hot ng l phi bo m xung clock bn ngoi c th ng b vi pha xung clock bn trong (TOSC). S khi ca Timer0 v WDT:

Cc h s chia H s chia dng cho Timer 0 hoc b WDT. Cc h s ny khng c kh nng c v kh nng vit. chn h s chia xung vo Timer0 hoc cho b WDT ta tin hnh xo hoc t bt PSA ca thanh ghi OPTION_REG<3> Nhng bt PS2, PS1, PS0 ca thanh ghi OPTION_REG<2:0> dng xc lp cc h s chia. Ngt ca b Timer0 Ngt ca b Timer 0 c pht sinh ra khi thanh ghi TMR0 b trn tc t FFh quay v 00h. Khi bt T0IF ca thanh ghi INTCON<2> s c t. Bt ny phi c xa bng phn mm nu cho php ngt bit T0IE ca thanh ghi INTCON<5> c set. Timer0 b dng hot ch SLEEP ngt Timer 0 khng nh thc b x l ch SLEEP.

Copyright (c) IRF Group *Thanh ghi OPTION_REG

bit 5 TOCS la chn ngun clock 1=Clock ngoi t chn T0CKI 0=Clock trong Focs/4 bit 4 T0SE bit la chon sn xung clock 1=Timer 0 tng khi chn T0CKI t cao xung thp(sn xung) 0=Timer 0 tng khi chn T0CKI t thp ln cao(sn xung) bit 3 PSA bit gn b chia xung u vo 1=gn b chia Prescaler cho WDT 0=gn b chia Prescaler cho Timer 0 bit 2:0 PS2:PS1 la chn h s chia xung vo theo bng sau PS2:PS0 Timer0 WDT 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1:16 1:8 100 1:32 1:16 101 1:64 1:32 110 1:128 1:64 111 1:256 1:128 2.5.2. B Timer 1 B Timer1 c th l b m hoc b nh thi vi u im sau: +16 bt cho b m hoc b nh thi (gm hai thanh ghi TMR1H:TMR1L). +C kh nng c v vit +C th chn xung ng h bn trong hoc ng h bn ngoi +C th ngt khi trn FFFFh v 0000h Timer1 c 1 thanh ghi iu khin, l thanh ghi T1C0N. B Timer1 c hot ng hay khng hot ng l nh vic t hoc xo bt TMR1ON(T1CON<0>). Hot ng ca b Timer1 N c th hot ng mt trong cc ch sau: + L 1 b nh thi 16 bit. + L mt b m c ng b . + L mt b m khng c ng b. Phng thc hot ng ca b ny c xc nh bi vic chn ngun xung vo Timer 1. Ngun xung ng h c chn bi vic t hoc xo bt TMR1CS (T1CON<1>). ch b nh thi, u vo l clock trong Fosc/4, bit ng b

Copyright (c) IRF Group T1SYNC(T1CON<2>) khng c tc dng v clock trong lun ng b. Ch b m hot ng hai ch : C ng b xung vo xo bit T1SYNC(T1CON<2>), khng ng b xung vo set bit T1SYNC(T1CON<2>) Timer 1 tng sn ln xung u vo. Khi b dao ng Timer1 cho php hot ng th cc chn RC1/T1OSI/CCP2, RC0/T1OSO/T1CKI tr thnh chn vo. ch m c ng b b m tng mi khi sn ln chn RC0 hoc chn RC1 nu bit T1OSCEN xo v xung vo phi ng b vi clock trong, ch ny b m khng tng trong trang thI SLEEP. ch m khng ng b Timer 1 tng mi khi sn ln chn RC0 hoc chn RC1 nu bit T1OSCEN xo, ch ny b m tip tc tng trong trang thi SLEEP v c kh nng trn gy ra ngt khi b s l c nh thc. Dao ng ca Timer1 Mch dao ng thch anh c xy dng gia 2 chn T1OSI v T1OS0. Khi dao ng c cung cp ch cng sut thp th tn s cc t ca n s l 200kHz v trong n ch SLEEP n cung cp tn s 32kHz Ngt ca b Timer1 Cp thanh ghi TMR1H v TMR1L tng t gi tr 0000h n gi tr FFFFh n gi tr ny tip tc tng th trn v quay li gi tr 0000h. V ngt xut hin khi trn qu gi tr FFFFh khi ny c ngt TMR1IF s c t. Ngt c th hot ng hoc khng hot ng nh vic t hoc xo bt TMR1IE

* Thanh ghi iu khin Timer1 T1CON:

Copyright (c) IRF Group

bt 7,6 khng s dng bit 5,4 T1CKPS1:T1CKPS0 la chn h s chia xung vo T1CKPS1:T1CKPS0 00 1:1 01 1:2 10 1:4 11 1:8 bit 3 T1OSCEN bit iu khin b dao ng Timer1 1= B dao ng hot ng 0= B dao ng khng hot ng bit 2 bit iu khin xung clock ngoi ng b khi TMR1CS=1 bit2=0 c ng clock ngoi =1 khng ng b clock ngoi khi TMR1CS=0 bit ny khng c tc dng bit 1 TMR1CS bit la chn ngun xung clock vo TMR1CS=1 clock t chn RC0/T1OSO/T1CKI(sn ln) TMR1CS=0 clock trong Fosc/4 Bit 0 bit bt tt Timer 1= Timer 1 enable 0=Timer 1 Disable 2.5.3. B Timer 2 B Timer2 c nhng c tnh sau y ; + 8 bt cho b nh thi ( thanh ghi TMR2 ) + 8 bt vng lp ( thanh ghi PR2 ) + C kh nng c v vit c hai thanh ghi ni trn + C kh nng lp trnh bng phn mm t l trc + C kh nng lp trnh bng phn mm t l sau Ch SSP dng u ra ca TMR2 to xung clock. Timer2 c mt thanh ghi iu khin l thanh ghi T2CON. Timer 2 c th tt bng vic xo bt TMR2CON ca thanh ghi T2CON Hot ng ca b Timer2 Timer 2 c dng ch yu phn iu ch xung ca b CCP, thanh ghi TMR2 c kh nng c v vit, n c th xa bng vic reset li thit b. u vo ca xung c th chn cc t sau ; 1:1 , 1:2 hoc 1:16 vic chn cc t ny c th iu khin cc bt sau T2CKPS1v bt T2CKPS0 Ngt ca b Timer2

Copyright (c) IRF Group B Timer2 c 1 thanh ghi 8 bt PR2 . Timer 2 tng t gi tr 00h cho n khp vi PR2 v tip theo n s reset li gi tr 00h v lnh k tip thc hin. Thanh ghi PR2 l mt thanh ghi c kh nng c v kh nng vit. Thanh ghi PR2 bt u t gi tr FFh u ra ca TMR2 l ng dn ca cng truyn thng ng b, n c dng pht cc xung ng h

* Thanh ghi T2CON

bit 7 khng s dng bit 6-3 TOUTPS3: TOUTPS0 bit la chn h s u ra Timer 2 0000=1:1 0001=1:2 0010=1:3 1111=1:16 bit 2 TMR2ON bit bt tt hot ng Timer 2 1= enable 0= disable bit 1- 0 T2CKPS1:T2CKPS0 chn h chia u vo 00 = 1:1 01 = 1:4 1x=1:16

Copyright (c) IRF Group 2.6. Truyn Nhn D Liu ng B, D B B truyn thng ng b, d b c th nh dng cc ch sau + d b (song cng ton phn) + ng b chnh (bn song cng) + ng b ph (bn song cng) y khi s dng truyn thng ng b hoc d b ta phi s dng bt SPEN ca thanh ghi RCSTA v bt 7,6 ca thanh ghi TRISC nh dng cc chn RC6/TX/CK v RC7/RX/DT 2.6.1. Tc truyn Tc truyn c cung cp cho c hai ch l truyn thng ng b v d b thanh ghi SPBRG iu khin chu k chy 8 bt ca timer. Trong ch d b ,bt BRGH ca thanh ghi TXSTA c dng Iu khin tc ,cn trong ch ng b n khng c s dng Cng thc tnh tc truyn: SYNC BRGH=0(Low speed) BRGH=1(High speed) 0 Asynchronous Synchronous (Baud rate=FOSC/(64*(X+1)) (Baud rate=FOSC/(16*(X+1)) 1 Synchronous Khng s dng (Baud rate=FOSC/(4*(X+1)) X l gi tr np vo thanh ghi SPBRG v d dng thch anh 20MHZ tc FOSC=20.000.000Hz c tc baud 9600 khi BRGH=1 l X= (20.000.000 (16 * 9600)) 1 = 129 np vo SPBRG *Thanh ghi iu khin v trng thi truyn

bit 7 CSRC bit la chn clock ch dng trong ch ng b 1= Master mode clock t BRG 0= Slave Mode clock t bn ngoi bit 6 TX9 cho php truyn 9 bit 1= truyn 9 bit 0=truyn 8 bit bit 5 TXEN bit cho phep truyn 1= cho php truyn 0=khng cho php truyn bit 4 SYNC la chn mode USART

Copyright (c) IRF Group 1= ng b 0= khng ng b khng s dng bit la chn tc cao 1=tc cao 0=tc thp TRMT cho trng thI thanh ghi dch TSR 1= TSR rng 0= TSR y TX9D D liu bit th 9 truyn i

bit 3 bit 2 bit 1 bit 0

*Thanh ghi iu khin v trng thi nhn

bit 7 SPEN cho php cng truyn ni tip 1= cho php hot ng 0=khng cho php bit 6 RX9 cho php nhn bit th 9 1= nhn 9 bit 0= nhn 8 bit bit 5 SREN Cho php nhn ring r Ch khng ng b v ch ng b ph bit ny khng s dng Ch ng b ch 0= khng cho nhn ring r 1= cho php nhn ring r bit 4 CREN cho php tip tc nhn ch khng ng b 1= cho php tip tc nhn 0= khng cho php tip tc nhn ch ng b 1= cho php tip tc nhn n khi bit CREN xo 0= khng cho php tip tc nhn bit 3 ADDEN Cho php nh a ch dng trong ch khng ng b truyn 9bit 1=Cho php nh a ch, bit RSR<8>l set cho php ngt np d liu vo m 0=nhn bnh thng bit 2 FERR bit li khung truyn 1= co li

Copyright (c) IRF Group 0= khng li bit 1 OERR bit li trn 1= c li trn 0=khng li trn bit 0 RX9D bit th c a vo y 2.6.2. Ch truyn thng khng ng b Trong ch ny d liu c nh dng nh sau: u tin l bt START , tip theo l 8 hoc 9 bt d liu, cui cng l bt STOP. Thng thng d liu c nh dng dng 8 bt. Vic truyn v nhn d liu c tin hnh vi nhng bt thp trc. Vic truyn v nhn c th tin hnh c lp nhau, khi s dng c th nh dng d liu v tc truyn. Vic truyn thng d b dng khi ch SLEEP *Truyn d liu ch di b Quan trng nht trong vic truyn d liu l thanh ghi TSR. D liu ca n c th c vit v c thng qua b m l thanh ghi TXREG. Thanh ghi TSR khng c np gi tr cho ti khi bt STOP ca ln trc chuyn i. Khi bt STOP chuyn i n s np gi tr mi ti thanh ghi TSR t thnh ghi TXREG. Nu thanh ghi TXREG rng n s t c bt TXIF ca thanh ghi PIR1. Trong khi c bt TXIF cho bit trng thi ca thanh ghi TXREG, th bt TRMT cho bit trng thi ca thanh ghi TSR. Bt trng thi TRMT ch dng c, n c t khi thanh ghi TSR rng. Vic truyn d liu hot ng khi ta t bt TXEN ca thanh ghi TXSTA. Vic truyn d liu ch hot ng khi d liu c np ti thanh ghi TXREG v tc truyn c sn sinh t xung ng h. Khi vic truyn d liu bt u ln u tin th thanh ghi TSR lc rng. Ngay lp tc d liu c truyn t thanh ghi TXREG ti thanh ghi TSR v sau thanh ghi TXREG rng, sau n li quay li nh trn. vic truyn 9 bt d liu I th bt truyn TX9 ca thanh ghi TXSTA phi c t v bt th 9 truyn i c vit ti bt TX9D. Bt th 9 ny phi c vit trc, trc khi chuyn 8 bt d liu ti thanh ghi TXREG. Bi v d liu vit ti thanh ghi ngay lp tc c chuyn ti thanh ghi TSR. *Vic nhn d liu ch d d b Trong ch d b, vic nhn d liu c kch hot bng vic t bt CREN ca thanh ghi RCSTA. Phn quan trng nht trong vic nhn d liu l thanh ghi RSR. Sau khi nhn xong bt STOP, n chuyn d liu t thanh ghi RSR ti thanh ghi RCREG nu thanh ghi ny trng. Nu vic truyn nhn hon thnh th c bt RCIF ca thanh ghi PIR1 s c t. c th ngt hot ng ca n bng vic t bt RCIE ca thanh ghi PIE1. C bt RCIF ch dng c, n c xa trong phn cng. N s c xo khi thanh ghi RCREG c c l trng. Thanh ghi ny l mt thanh ghi c b m i. N c kh nng nhn 2 byte d liu v truyn ti thanh ghi RCREG FIFO v khi byte th 3 i vo thanh ghi RSR. Nu pht hin bt STOP m thanh ghi RCREG vn y th bt bo li OERR s c t. Bt bo

Copyright (c) IRF Group li ch c xo trong phn mm. Nu bt OERR c t th vic truyn d liu t thanh ghi RSR ti thanh ghi RCREG b ngn cm v khng c d liu c nhn. Cu trc ca bt bo li FERR c t khi bt STOP c pht hin c xo. Bt FERR v bt th 9 l cc b m ging nh phng php b m. Trong khi ang c thanh ghi RCREG n s np gi tr mi cho bt RX9D v FERR 2.6.3. Truyn thng ng b ch ch Trong ch d ny d liu c truyn nhn dui dng bn song cng (vic truyn v nhn d liu khng th tin hnh ng thi cng mt lc). Khi ang truyn d liu th vic nhn d liu b ngn cm. vic chn ch truyn thng ng b c xc lp bng vic t bt SYNC ca thanh ghi TXSTA, ngoi ra bt SPEN cn c t nh dng cc chn RC6/TX/CKv RC7/RX/DT cho chn xung ng h v chn truyn d liu. Ch ch cn c xc lp bng vic t bit CSRC ca thanh ghi TXSTA. Vic nhn d liu trong ch truyn thng ng b ch. Tng t nh truyn thng d b, n phi c thanh ghi TSR. thanh ghi ny c v vit d liu thng qua b m l thanh ghi TXREG. Thanh ghi ny c np d liu trong phn mm. Thanh ghi TSR s khng c np gi t cho ti tn thi truyn ht bt cui cng ca ln truc . Khi truyn ht bt cui cng, th thanh ghi TSR s np gi tr mi t thanh ghi TXREG. Thanh ghi TXREG rng th bt c ngt TXIF s c t. C ngt ny c th quy nh hot ng hoc khng hot ng bng vic t hoc xo bt TXIE ca thanh ghi PIE1. Trong khi c bt TXIF cho bit trng thi ca thanh ghi TXREG, th bt TRMT cho bit trng thi ca thanh ghi TSR. Bt trng thi TRMT ch dng c, n c t khi thanh ghi TSR rng. Vic truyn d liu hot ng bng vic t bt TXEN ca thanh ghi TXSTA, bt d liu u tin s c di chuyn trn xung i ln ca xung clock trn chn CLK. Vic truyn d liu c bt u bng thanh ghi TXREG v t bt TXEN. u im y l tc thp c th c la chn. Tc truyn c gi nguyn trong khi RESET khi xo 3 bt TXEN, CREN, SREN. Vic truyn d liu c bt u ln u tin khi thanh ghi TSR rng, khi chuyn d liu ti thanh ghi TXREG n ngay lp tc chuyn ti thanh ghi TSR v kt qu l thanh ghi TXREG rng. Xo bt TXEN Trong khi ang truyn d liu l l do vic truyn d liu b gin on v n phi dng li, v nu bt CREN hoc bt SREN c t trong khi ang truyn cng l nguyn nhn gy ra vic truyn d liu b gin on. Vi mc ch truyn 9 bt d liu th bt TX9 ca thanh ghi TXSTA phi c t v bt th 9 ny phi c vit ti bt TX9D. Bt th 9 ny phi c vit trc khi vit 8 bt d liu ti thanhghi TXREG. Bi v d liu c vit ti thanh ghi TXREG ngay lp tc c chuyn ti thanh ghi TSR, nu thanh ghi ny rng. Nu thanh ghi TSR rng v thanh ghi TXREG c vit trc khi vit gi tr mi ti bt TX9D, th hin ti n s np gi tr c trong bt TX9D.

Copyright (c) IRF Group Vic nhn d liu ch ng b ch: ch nhn d liu ch ng b ch c chn bng vic t bt SREN hoc bt CREN ca thanh ghi RCSTA. D liu c a chn RC/RX/DT trn cnh xung ca xung ng h. Nu bt SREN c t th ch c 1 t c nhn. nu bt CREN c t th vic nhn c tip din cho ti tn khi bt ny c xo mi thi. C hai bt ny u c t th bt CREN c u tin trc ri theo th t . Sau khi d liu c nhn vo trong thanh ghi RSR n s chuyn ti thanh ghi RCREG. Khi vic chun dch ny hon thnh th c bt RCIF ca thanh ghi PIR1 s c t. Hot ng ca c ny c th c hoc khng nh vic t hoc xo bt RCIE ca thanh ghi PIE1. RCREG l 1 thanh ghi c 2 b m l 2 thanh ghi. N c kh nng nhn 2 byte d liu chuyn ti thanh ghi RCREG FIFO v byte th ba bt u chuyn ti thanh ghi RSR. Trong khi ri bt cui cng ca byte th ba m thanh ghi RCREG vn y th bt bo li OERR s c t va t trong thanh ghi RSR s b li. Bt OERR c xa trong phn mm. Nu bt ny c t th vic chuyn d liu t thanh ghi RSR ti thanh ghi RCREG b ngn cm. Vic nhn bt th 9 cng tng t nh vic nhn bt d liu. Trong khi thanh ghi RCREG ang c n s np gi tr mi cho bt RX9D. l Iu cn ch khi ngi s dng dng truyn thng chn bt d liu 2.6.4. Truyn thng ng b ch ph Truyn thng ng b ch ph khc vi truyn thng ng b ch chnh trong trng hp xung ng h bn ngoi cung cp ti chn RC6/ TX / CK. N c th cho php thit b nhn hoc truyn d liu trong ch SLEEP. Ch ph c tin hnh bng vic xo bt CSRC ca thanh ghi TXSTA. *Truyn d liu trong ch truyn thng ph: Hot ng ca ch truyn thng ng b chnh v truyn thng ng b ph hon ton ging nhau, ch khc l ch truyn thng ph c th hot ng ch SLEEP. Nu hai t c vit ti thanh ghi TXREG v lnh SLEEP c tin hnh th n s tn ti nhng im sau : +T u truyn ti thanh ghi TSR v n chuyn i ngay lp tc +T th hai c cha trong thanh ghi TXREG +C bit TXIF s khng c t +Khi t u tin c chuyn ra khi thanh ghi TSR. Thanh ghi TXREG s chuyn t th hai vo thanh ghi TSR v by gi c bt TXIF s c t +Nu bt TXIE c t ngt s c gi t SLEEP v ngt tnh ton cu ca ngt s c gi. Khi thit lp Truyn thng ng b ch ph ta c nhng bc sau: + thit lp ch cng truyn thng ng b ph th ta phi t bt SYNC v Bt SPEN v xo bt CSRC + Xo bt CREN v SREN + Nu ngt c th hot ng, th phi t bt TXIE + Nu truyn thng chn bt th phI t bt TX9 +Vic truyn thng c th thit lp TXEN

Copyright (c) IRF Group + Nu vic truyn thng chn bit c thit lp th bt th chn phI c np ti bt TX9D +Khi mi bt u truyn th d liu c np ti thanh ghi TXREG + Nu s dng ngt th phI chc chn rng bt GIE v bt PEIE c t *Nhn d liu ch truyn thng ng b ph: Hot ng ca ch truyn thng ng b ch ph v truyn thng ng b ch chnh hon ton ging nhau, nhng ch ph n c th hot ng lnh SLEEP. Bt SREN khng c s dng ch ny. Nu vic nhn d liu c hot ng bng vic t bt CREN trc khi lnh SLEEP c thc hin. T c nhn trong khi SLEEP, khi vic nhn d liu hon thnh, th thanh ghi RSR s chuyn d liu ti thanh ghi RCREG V nu bt RCIE c t, th ngt c th gi t lnh SLEEP. 2.7. B chuyn i tng t sang s : B chuyn i tng t sang s c 8 knh i Pic16F877. Tn hiu tng t c np vo b np in v gi in dung. Tn hiu ra in hnh v gi in dung duy tr l u vo b chuyn i. B chuyn i A/D pht ra kt qu s 10 bt. B chuyn i A/D c s chuyn in th cao v thp u vo c la chn trong phn mm c s kt hp ca VDD, VSS, RA2, RA3. B chuyn i A/D c c trng duy nht c th hot ng trong khi thit b l trong trng thi SLEEP. hot ng trong phng thc ny A/D phi c ly t ngun ng h bn trong mch dao ng RC. B chuyn i A/D c 4 thanh ghi. l nhng thanh ghi: A/D thanh ghi kt qu cao(ADRESH) A/D thanh ghi kt qu thp(ADRESL) Thanh ghi iu khin chuyn i A/D ( ADCON0) Thanh ghi iu khin chuyn i A/D ( ADCON1) Thanh ghi ADCON0 trnh by trong thanh ghi 8.1 iu khin hot ng ca b chuyn i A/D. Thanh ghi ADCON1 trnh by trong hnh 8.2 nh dng hm ca chn cng. Chn cng c th sp xp nh l tn hiu vo tng t hoc nh l u vo ra s. *Thanh ghi 8.1: Thanh ghi ADCON0 ( a ch 1Fh) Bt 7-6: ADCS1:ADCS0 Nhng bt la chn ng h chuyn i A/D 00=FOSC/2 01= FOSC/8 10= FOSC/32 11= FRC(ng h xut pht t bn trong b chuyn i A/D dao ng RC) Bt 5-3:CHS2:CHS0 Bt chn knh tng t. 000=knh 0( RA0/AN0) 001=knh 1 (RA1/AN1) 010=knh 2 (RA1/AN2)

Copyright (c) IRF Group 011=knh 3 (RA3/AN3) 100=knh 4 (RA5/AN4) 101=knh 5 ( RE0/AN5) 110=knh 6 (RE1/AN6) 111=knh 7( RE2/AN7) Bt 2 :GO/DONE bt trng thi chuyn i A/D Nu ADON=1 1=chuyn i A/D ang thc hin (t bt ny bt u qu trnh chuyn i) 0=chuyn i A/D khng trong qua trnh thc hin(Bt ny s t ng xo bi phn cng sau khi qu trnh chuyn i A/D hon thnh.) Bt 1: Bt ngi dng nh ngha . Bt 0: ADON:bt bt chuyn i. 1= B chuyn i A/D hot ng 0=B chuyn i A/D tt v ngng hot ng. *Thanh ghi 8.2 thanh ghi ADCON1(a ch 9Fh) Bt 7 : ADFM : bt la chn kt qu nh dng . Bt 6-4 : ngi dng nh ngha . Bt 3-0 : Bt iu khin sp xp cng chuyn i A/D. Thanh ghi ADRESH:ADRESL cha ng 10 bt kt qu ca chuyn i A/D. Khi chuyn i A/D l hon thnh kt qu c np vo thanh ghi kt qu chuyn i A/D. Bt GO/DONE (ADCON0<2>) c xo v bt c ngt chuyn i A/D l ADIF c t. Sau b chuyn i A/D c sp xp nh mong mun. La chn knh phi t c trc khi chuyn i bt u. Knh vo tng t phi c bt TRIS tng ng c la chn nh l u vo. Nhng bc cn lm theo khi thc hin chuyn i A/D : 1. la chn cu hnh A/D +t cu hnh tng t cho chn vo A/D +La chn knh vo chuyn i A/D (ADCON0) . +La chn ng h chuyn i A/D . +Bt b chuyn i A/D (ADCON0) . 2. La chn cu hnh ngt cho A/D +Xo bt ADIF. +t bt ADIE. +t bt PEIE. +t bt GIE 3. i ph thuc thi gian t c. 4. Bt u chuyn i: +t bt GO/DONE(ADCON0). 5. i cho chuyn i A/D hon thnh bi : +Thm d bt GO/DONE xo (vi thc hin ngt) hoc i cho ngt chuyn i A/D.

Copyright (c) IRF Group 6. c kt qu chuyn i cp thanh ghi (ADRESH:ADRESL) xo bt ADIF nu quy nh . 7. Cho chuyn i k tip, thc hin bc 1 hoc bc 2 theo quy nh.Tc chuyn i A/D qui nh nh l chu k TAD. Gi tr nh nht i ca 2 chu k l c quy nh trc khi bt u k tip. 2.7.1. La chn tc chuyn i : Tc chuyn i l c nh nh l TAD. Quy nh thi gian chuyn i A/D nh nht 12TAD cho 10 bt chuyn i. Ngun ca thi gian chuyn i la chn trong phn mm. C th chn mt trong 4 bng la chn. 2TOSC , 8TOSC, 32TOSC, Dao ng RC trong b chuyn i A/D.(2n 6 s). cho vic chuyn i ng ,thi gian chuyn i TADphi c la chn chc chn TADnh nht 1.6 s. Bng 11-1 trnh by gi tr thi gian TAD nhn c t thit b pht tn s v la chn ngun ng h . Ch : 1>Ngun RC c thi gian chu k TAD4 s nhng c th trong khong 2 6 s. 2>Khi tn s thit b ln hn 1MHz b chuyn i A/D ngun ng h khi to cho SLEEP hot ng. 2.8. Cc ngt ca PIC16F877 PIC16F877 c 14 ngun ngt, thanh ghi INTCON l thanh ghi iu khin cc ngt, mi ngt c mt bit c ngt v mt bit cho php hoc cm ngt. Bit GIE (INTCON<7>) iu khin chung cho 14 ngt khi bit ny set th cc ngt mi c tc dng, khi bit GIE xo th tt c cc ngt b cm. Bit GIE b xo khi reset. Khi bit c ngt thit lp bit GIE thit lp v bit PEIE thit lp vi ngt ngoi vi ng thi bit cho php ngt ca ngt cho php th ngt xy ra. Khi mt ngt xy ra b m chng trnh PC c np gi tr 0004h v bit GIE b xo cm s chng ngt, khi ch lnh RETFIE thc hin tr li a ch cho PC ni xy ra ngt, ng thi thit lp li bit GIE. Khi xy ra ngt PC lun c np gi tr 0004h v cc ngt c phn bit bi bit c ngt ca ngt . Ngt ngoi t chn RB0/INT, v ngt t s thay i trng thi cc chn RB4:RB7 c th nh thc b x l t ch SLEEP. Cc thanh ghi PIE1, PIR1, PIE2, PIR2 iu khin cc ngt ngoi vi S cc bit iu khin ngt:

Copyright (c) IRF Group

Khi mt ngt xy ra ch c PC c lu trong stack do ngi s dng phi lu cc thanh ghi W, STATUS, PCLATH, khi xy ra ngt. v d thc hi iu ny: ORG 0000h ... ORG 0004h MOVWF W_TEM ;Lu W MOVF STATUS,W CLRF STATUS ;chon bank 0 MOVWF STATUS_TEM ;Lu STATUS MOVF PCLATH,W MOVWF PCLATH_TEM ;Lu PCLATH CLRF PCLATH ;chn trang 0 ... ;chng trnh phc v cc ngt ... ;Khi phc cc thanh ghi CLRF STATUS MOVF PCLATH_TEM,W MOVWF PCLATH

Copyright (c) IRF Group MOVF STATUS_TEM,W MOVWF STATUS MOVF W_TEM,W RETFIE Ch bin W_TEM phi c nh nghia tt c cc bank hoc vng a a chung cho cc bank( PIC16F877 l a ch 70h-7Fh), cc bin PCLATH_TEM, STATUS ch nh ngha bank 0. 2.9. M t tp lnh ca PIC16F877. PIC16F877 c 35 lnh hu ht cc lnh thc hin trong mt chu k my tr mt s lnh r nhnh. Mi lnh lun c di c nh 14 bit. Quy c f: a chi nh t 0-7fh d: bit nh hng d liu kt qu +d=1 kt qu lu trong f +d=0 lu trong W b: ch ra bit th b trong f, 0=<b<=7 k: hng s t 0-ffh Bng tp lnh PIC16F877. Tn lnh gi nh ADDWF f,d ANDWF f,d CLRF f CLRW COMF f,d DECF f,d DECFSZ f,d INCF f,d INCFSZ f,d IORWF f,d MOVF f,d MOVWF f NOP RLF f,d RRF f,d SUBWF f,d SWAPF f,d XORWF BCF BSF f,d f,b f,b M t lnh Cng W vi f AND W v f Xo nh,thanh ghi f Xo W Ly b 1 ca f Gim f mt n v Gim f mt n v, skip if 0 Tng f mt n v Tng f mt n v, skip if 0 Or W v f Copy f ti W hoc chnh f Copy W ti f Khng lm g Quay tri f qua c nh C Quay phi f qua c nh C Tr f cho W Hon v 4 bit thp ca f cho 4 bit cao ca f Xor W v f Xo bit b ca f Set bit b ca f S chu k lnh 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 Trng thi c nh hng C,DC,Z Z Z Z Z Z Z Z Z C C Z,DC,C Z

Copyright (c) IRF Group BTFSC BTFSS ADDLW ANLW CALL f,b f,b k k k Test bit b ca f, Skip if clear Test bit b ca f, Skip if set W=Cng k v W W=WAnd k Gi th tc con a ch k l s 11 bit Reser WDT Nhy ti a ch k l s 11 bit W=W or k W=k Tr v t ngt Tr v t th tc con v W=k Tr v t th tc con Nhy ti ch ng W=k-W W=W xor k 1(2) 1(2) 1 1 2 1 2 1 1 2 2 2 1 1 1

Z,DC,C Z

CLRWDT GOTO k IORLW k MOVLW k RETFIE RETLW k RETURN SLEEP SUBLW k XORLW k

TO , PD

TO , PD

Z,DC,C Z

Skip if 0: Nu kt qu =0 th b qua mt lnh ngay sau lnh ny Skip if clear: bit ny xo thi b mt lnh ngay sau lnh ny Skip if set: bit ny set thi b mt lnh ngay sau lnh ny Nguyn Vn Xun Mail: nvxuan@irfvn.com