Digital Electronics Lab Manual

DIGITAL ELECTRONICS LAB
OBSERVATION NOTE BOOK
FOR
DIGITAL ELECTRONICS
LABORATORY
Name of the Student : .. Reg. No. / Roll No. : ... Degree & Branch : ...
VIDYAA VIKAS COLLEGE OF ENGG & TECH
INSTRUCTIONS
The students are required to get the approval from the lab in charge within the first 15 minutes.
The approval is given for the students who have recorded the Aim of the Experiment, Apparatus required, Theory, Procedure, Circuit diagram and the Truth Table in the Observation.
The students can proceed with the Experiment only after the above approval.
Verification is required from the Lab In Charge after the completion of the experiment.
Verified Experiments are to be recorded in the record file and can be submitted in the next class.
CONTENTS S.NO 1 NAME OF THE EXPERIMENT Transfer characteristics and specifications of TTL & MOS gates. 2 Verification of Laws & Theorems and realization of circuits for Boolean expression after simplification. 3 Design of Half adder, Full adder and Subtractors using NAND Gates. 4 Design of RS and JK Flip flops using NAND Gates. 5 Design of code converters (GREY to BCD & vice versa, excess-3 code etc). 6 7 8 Design of Parity generator. Design of Decoders and Encoders. Design of Synchronous Counters (Up, Down, &BCD). 9 Design of Asynchronous Counters (Up, Down, &BCD). 10 11 12 Shift Registers (all types). Design of Ring Counters. Multiplexer and Demultiplexer and extensions(e.g. 4 to 8) 13 Binary Addition/Subtraction, a. 1s complement b. 2s complement 14 Memories. PAGE.NO SIGNATURE
EX.NO: 1
TRANSFER CHARACTERISTICS AND SPECIFICATIONS OF TTL & MOS GATE
DATE: AIM: To find the Transfer characteristics and Specifications of TTL & MOS Gates.
APPARATUS REQUIRED:
SPECIFICATION/ RANGE IC7400 1k, 4k, 1.6k, 130,
Sl.No. 1 2 3 4 5
COMPONENTS NAND GATE Resisters
Qty 2 1
Digital Trainer Kit Digital Power Supply
(0 12) V (0 5) V
1 1
THEORY: TTL can be noticed that Q1 is an NPN transistor having two emitters, one for each input to the gate. Although this circuit looks complex, we can simplify its analysis by using the diode equivalent of the multiple-emitter transistor Q1. Diodes D2 and D3 represent the two E-B junctions of Q1 and D4 is the collector-base (C-B) junction. The input voltages A and B are either LOW (ideally grounded) or HIGH (ideally +5volts). If either A or B or both are low, the corresponding diode conducts and the base of Q1 is pulled down to approximately 0.7v. This reduces the base voltage of Q2 to almost zero. Therefore, Q2 cuts off. With Q2 open, Q4 goes into cutoff, and the Q3 base is pulled HIGH. Since Q3 acts as an emitter follower, the Y output is pulled up to a HIGH voltage. On the other hand, when A and B both are HIGH, the emitter diodes of Q1 are reversed biased making them off. This causes the collector diode D4 to go into forward conduction. This forces Q2 base to go HIGH. In turn, Q4 goes into saturation, producing a low output. Table summarizes all input and output conditions. Without diode D1, in the circuit, Q3 will conduct slightly when the output is low. To prevent this, the diode is inserted; its voltage drop keeps the base-emitter diode of Q3 reverse-biased. In this way, only Q4 conducts when the output is low.

CIRCUIT DIAGRAM:
TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0
CMOS NAND Gate: CMOS 2 input NAND gate. It consists of two P-channel MOSFETs, Q1 and Q2, connected in parallel and two N-channel MOSFETs, Q1 and Q4 connected in series. P-channel MOSFET is ON when its gate voltage is negative with respect to its source whereas N-channel MOSFET is ON when its gate voltage is positive with respect to its source. The equivalent switching circuit when both inputs are low. Here, the gates of both P-channel MOSFETs are negative with respect to their courses, since the sources are connected to + VDD . Thus Q1 and Q2 are both ON. Since the gate-tosource voltages of Q3 and Q4 (N-channel MOSFETs) are both 0v, those MOSFETs are OFF. The output is therefore connected to + VDD (HIGH) through Q1 and Q2 and is disconnected from ground, the equivalent switching circuit when A=0 and B=+ VDD . In this case, Q1 is on because + VGS1=- VDD and Q4 is ON because + VGS4=+ VDD. MOSFETs Q2 and Q3 are off because their gate-to-source voltages are 0v. Since
Q1 is ON and Q3 is OFF, the output is connected to + VDD and it is disconnected from ground. When a=+ VDD and B=0v, the situation is similar (not shown); the output is connected to + VDD through Q2 and it is disconnected from ground because Q4 is OFF. Finally, when both inputs are high (A=B=+ VDD), MOSFETs Q1 and Q2 are both OFF and Q3 and Q4 are both ON. Thus, the output is connected to the ground through Q3 and Q4 and it is disconnected from + VDD. The table summarizes the operation of 2-input CMOS NAND gate. CIRCUIT DIAGRAM
TRUTH TABLE:
A 0 0 1 1
B Q1 Q2 Q3 Q4 Output 0 ON ON OFF OFF 1 1 ON OFF OFF ON 1 0 OFF ON ON OFF 1 1 OFF OFF ON ON 0
PROCEDURE: 1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table. 3. Check for the output as given in the characteristics table by the glowing of LED.
Result:
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Ex. No: 2
DATE:
VERIFICATION OF LAWS & THEOREMS AND REALIZATION OF CIRCUITS FOR BOOLEAN EXPRESSION AFTER SIMPLIFICATION
AIM: To Verify the Boolean theorem using logic gates.
APPARATUS REQUIRED:
Sl.No. 1 2 3 4 5 COMPONENTS AND Gate OR Gate NOT Gate Digital IC Trainer Digital Power Supply SPECIFICATION/ RANGE IC7408 IC7432 IC7404 IC 7486 IC 7400 Qty 1 1 1 1 1
THEORY: One of the primary requirements when dealing with digital circuits is to find ways to make them as simple as possible. This constantly requires that complex logical expressions be reduced to simpler expressions that nevertheless produce the same results under all possible conditions. The simpler expression can then be implemented with a smaller, simpler circuit, which in turn saves the price of the unnecessary gates, reduces the number of gates needed, and reduces the power and the amount of space required by those gates. One tool to reduce logical expressions is the mathematics of logical expressions, introduced by George Boole in 1854 and known today as Boolean Algebra. The rules of Boolean Algebra are simple and straightforward, and can be applied to any logical expression. The resulting reduced expression can then be readily tested with a Truth Table, to verify that the reduction was valid.
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The rules of Boolean Algebra are: AND Operations () 00 = 0 10 = 0 01 = 0 11 = 1 0+0 = 0 1+0 = 1 0+1 = 1 1+1 = 1 0' = 1 1' = 0 Associative Law (AB)C = A (BC) = ABC (A+B)+C = A+ (B+C) = A+B+C Distributive Law A (B+C) = (AB) + (AC) A+ (BC) = (A+B) (A+C) Commutative Law AB = BA A+B = B+A Precedence AB = AB AB+C = (AB) + C A+BC = A + (BC) DeMorgan's Theorem (AB)' = A' + B' (NAND) A0 = 0 A1 = A AA = A AA' = 0 A+0 = A A+1 = 1 A+A = A A+A' = 1 A = A
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OR Operations (+)
NOT Operations (')
(A+B)' = A' B' (NOR)

Expression => X=W+PQ X= W+PQ = W.PQ = W.PQ = W.PQ
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12
CIRCUIT DIAGRAM
12
13
OR GATE
SYMBOL
A B
1 3 2
TRUTH TABLE A B 0 1 0 1 Y= A+B 0 1 1 1
7432
Y= A+B
0 0 1 1
PINDIAGRAM
VCC
14 13 12 11 10 9 8
12 11 13
9 8 10
IC7432
1 3 2 5 4 6
GND
AND GATE
TRUTH TABLE SYMBOL
A B
1 2
A 0
B 0 1 0 1
Y = A.B 0 0 0 1
7408
Y = A.B
0 1 1
PIN DIAGRAM
VCC 14 13 12 11 10 9 8
12 11 13
9 8 10
IC7408
1 3 2 5 4 6
7 GND
13
14
NOT GATE
SYMBOL ___ Y= A A 0 1
PINDIAGRAM
VCC 14 13 12 11 10 9 8
TRUTH TABLE __ Y= A 1 0
7404
13
12
11
10
IC7404
1 2 3 4 5 6
7 GND
NAND GATE
SYMBOL A B
1 2
TRUTH TABLE ____ Y= A.B A 0 0 1 1 B 0 1 0 1 _____ Y= A.B 1 1 1 0
7400
PINDIAGRAM
VCC
14 13 12 11 10 9 8
12 11 13
9 8 10
IC7400
1 3 2 5 4 6
GND
14

NOR GATE
SYMBOL A B
2 1 3
15
7402
______ Y= A+B A 0 0 1 1
TRUTH TABLE B 0 1 0 1 _____ Y= A+B 1 0 0 0
PINDIAGRAM
VCC 14 13 12 11 10 9 8
12 13 11 10
9 8
7402
3 1 2 4 5 6
7 GND
EXOR GATE
TRUTH TABLE
7486
3
A B
1 2
Y= A + B A 0 0 1 1 B 0 1 0 1 Y= A + B 0 1 1 0
PINDIAGRAM
VCC
14 13 12 11 10 9 8
12 11 13
9 8 10
IC7486
1 3 2 5 4 6
GND
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PROCEDURE: 1. For the above given functions form the truth table. 2. Using basic Gate implements the function. 3. Verify the truth table.
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RESULT:
QUESTIONS: 1. 2. 3. 4. Define Boolean Algebra. State the Boolean theorems State the Duality theorem State the Boolean Law.
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Ex. No: 3 Date: DESIGN HALF ADDER, FULL ADDER AND SUBTRACTORS USING NAND GATES
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AIM:
To design and construct Half adder, Full adder, Half subtractor and Full subtractor using Logic gates and verify the truth table.
APPARATUS REQUIRED:
Sl.No. 1 2 3 COMPONENTS NAND Gate Digital Trainer Kit Digital Power Supply SPECIFICATION/ RANGE IC 7400 (0 12) V (0 5) V Qty 10 1 1
HALF ADDER
THEORY: A basic module used in binary arithmetic elements is the half adder. The function of half adder is adding two binary digits producing a sum and carry. These are two inputs to the half adder designated sum and carry .The half adder performs binary addition operation for two binary inputs. This is Arithmetic addition, not logical and Boolean addition. If either of the inputs is a 1 but not both, the output on the Sum will be 1. If both the inputs are 1s then the output on the C will be 1 .for other states, there will be a 0 output on the carry line. The relationship can be written as Sum = AB AB
Carry =
TRUTH TABLE
A 0 0 1 1
B 0 1 0 1
S 0 1 1 0
C 0 0 0 1
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CIRCUIT DIAGRAM:
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AB
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FULL ADDER:
THEORY:
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A full adder is the combinational circuit that forms the arithmetic sum of three input bits. The full adder accepts three inputs and generates a sum output and carries output. The relationship can be written as Sum = (A B) C AB + (A + B) C
Carry =
The full Adder can be constructed using two Half Adders and an AND Gate
TRUTH TABLE:
C 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
A 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
C 0 0 0 1 0 1 1 1
CIRCUIT DIAGRAM:
AB
ABC
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HALF SUBTRACTOR:
THEORY:
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A Half Subtractor is a combinational circuit that subtracts two bits and produces their difference .It also has an output to specify if a 1 has been borrowed. Designate the minuend bit by X and the subtrahend bit by Y.To perform X - Y, we have to check the relative magnitude of X and Y. The result is called difference bit .The half subtractor needs two outputs .One output generates the difference and will be designated by the symbol D. The second output, designated B for borrow, generates the binary signal that informs the next stage that a 1 has been borrowed CIRCUIT DIAGRAM: TRUTH TABLE
x y
1
1 2
D=X+Y
1 2
B=X'Y
HALF-SUBTRACTOR Truth Table 3.2.1
X 0 0 1 1
Y 0 1 0 1
D 0 1 1 0
B 0 1 0 0
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21
D= X Y
B=X Y
FULL SUBTRACTOR
THEORY A full subtractor is a combinational circuit that performs the subtraction between two bits, taking into account that 1 has been borrowed by a lower significant stage. The circuit has three inputs and two outputs .The three inputs X, Y, Z denotes the minuend, subtrahend and previous borrow respectively .The two outputs D and B represents the difference and output borrow respectively TRUTH TABLE:
Input Z 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 Y 0 1 0 1 0 1 0 1
Output D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1
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CIRCUIT DIAGRAM:
x
1 1
1 2 4 5 9 10
AND2 AND2 AND2
3 1 2 6 5
OR2 OR2
3 4
7432
B=X'Y+X'Z+YZ
4 5 1 2 3
XOR2
D=X+Y+Z
X Y
XY
Z B
D=XYZ B=(XY)Z+XY
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PROCEDURE:
1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table. 3. Check for the output as given in the characteristics table by the glowing of LED. 4. Draw the conclusion.
RESULT:
QUESTIONS:
1. What is a Half Adder? Design and implement it using NOR gate. 2. Define Combinational circuit. 3. Show by Boolean Function how a Full Adder can be constructed by two Half Adder and an OR gate. 4. What is a Half Subtractor? Design and implement it using NOR gate? 5. Show by Boolean Function how a Full Subtractor can be constructed by two Half Subtractor and an OR gate?
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Ex. No: 4 Date: AIM:
To construct flip-flops like RS flip-flop,JK flip-flop to verify their truth table.
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DESIGN OF RS AND JK FLIP FLOPS USING NAND GATES
APPARATUS REQUIRED:
Sl.No. 1 2 3 4 5 6 7 COMPONENTS NAND GATE 3 INPUT AND GATE 2 INPUT AND GATE NOT GATE NOR GATE Digital Trainer Kit Digital Power Supply SPECIFICATION/ RANGE IC7400 IC7411 IC7408 IC7404 IC7402 (0 12) V (0 5) V Qty 1 2 1 1 1 1 1
RS FLIP FLOP
THEORY A flip-flop circuit can maintain a binary state indefinitely (as long as the power is delivered to the circuit) until directed by the input signal to switch states .the major differences among various types of flip flops are in number of inputs they possess and in the manner in which the inputs affects the binary state A flip-flop can be constructed from two NAND gates or two OR gates .The cross coupled connection from the output of one gate to the input of other gate constitutes a feedback path .for this reason the circuits are called as asynchronous sequential circuits each flip-flop has two outputs, Q and Q, and two inputs, set and reset This type of flip-flop is sometimes called direct coupled RS flip-flop or SR latch .To analyze the operation of the circuit, we must remember that output of an NOR Gate is0 if any input is 1 ,and the output is 1 only when all the inputs are 0 .At the starting point assume the set input is 1 and the reset input is 0.Since gate 2 has an input of 1 ,its output Q must be 0 ,which puts both inputs of gate 1at 0,so that output Q is 1 .When the set input is returned to 0,the outputs remain the same ,because the output Q remains a 1 ,leaving one input of gate 2 at 1.this causes output Q to stay at
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0 which leaves both inputs of gates number 1 at 0 ,so the output Q is a1 . In the same manner it is possible to show that a 1 in the reset input changes Q to 0 and Q to 1. When the reset input returns to 0 the output do not change. When a 1 is applied to both the set and the reset inputs, both Q and Q outputs go to 0. This condition violates the fact that outputs Q and Q are the complements of each other. In normal operation, this condition must be avoided by making sure that 1s are not applied to both inputs simultaneously.
PINDIAGRAM:
TRUTH TABLE:
S 1 0 0 0 1
R 0 0 1 0 1
Q 1 1 0 0 0
Q 0 0 1 1 0
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CIRCUIT DIAGRAM:
26
JK FLIP-FLOP
THEORY A JK flip flop is a refinement of the RS flip flop in that the indeterminate state of the RS type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop respectively .The input marked J is for set and the input marked k is for Reset. When both inputs J and K are equal to 1, the flip-flop switches to its complement state, that is if Q=1 it switches to Q=0 and vice versa.
PINDIAGRAM
26

TRUTH TABLE:
27
J 0 0 1 1
K 0 1 0 1
Q(t+1) Q(t) 0 1 Q(t)
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table. 3. Check for the output as given in the characteristics table by the glowing of LED. 4. Draw the conclusion.
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RESULT:
QUESTIONS:
1. Define sequential circuit. 2. What is a flip-flop? 3. What is the difference in the implementation of RS flip-flop using NAND and NOR gate? 4. Define characteristic table. 5. Explain triggering. Give the difference between positive and negative edge triggering?
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Ex. No: 5 DESIGN OF CODE CONVERTERS (GREY to BCD & Vice versa, Excess-3 code etc) DATE: AIM: To design and verify the operations of Binary to Gray code converter, Gray to Binary code converter, BCD to Excess 3 code converter and Excess 3 to BCD code converter using Logic gates. APPARATUS REQUIRED: S.NO 1 2 3 4 5 6 COMPONENTS OR GATE EXOR GATE AND GATE NOT GATE DIGITAL TRAINER KIT DIGITAL POWER SUPPLY SPECIFICATION/RANGE IC7432 IC7486 IC 7408 IC7404 (0-12) V (0-5) V QUANTITY 1 1 1 1 1 1
THEORY: The communication systems requires various types of data codes for security purposes, so we need some code converters to convert the actual data into some other form. The commonly used code converters are binary code to gray code and BCD to Excess 3 code and vice versa converters. Binary code to Gray code converter: Gray code is a one bit change code which is used in many decoding applications like Optical shaft encoders. This circuit accepts a 4-bit binary code input and converts into its equivalent 4 bit gray code. BCD code to Excess-3 code converter: Excess 3 code means adding the binary value 011(i.e., 3d) to the original data. BCD stands for Binary Coded Decimal, it is a number system rages from the decimal values 0 and 9. This circuit accepts the 4-bit BCD value and converts into its equivalent 4 bit Excess-3 code.
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CIRCUIT DIAGRAM: 1. BINARY TO GRAY CODE CONVERTER:
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TRUTH TABLE: Input Binary Code B4 B2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Output Gray Code G1 G2 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0
B8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
G0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
G3 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
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2. GRAY TO BINARY CODE CONVERTER:
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TRUTH TABLE: Input Gray Code G1 G2 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 Output Binary Code B4 B2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
G0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
G3 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
B8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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3. BCD TO EXCESS-3 CODE CONVERTER:
TRUTH TABLE: Output Excess-3 code B0 0 0 0 0 0 0 0 0 1 1 B1 0 0 0 0 1 1 1 1 0 0 B2 0 0 1 1 0 0 1 1 0 0 B3 0 1 0 1 0 1 0 1 0 1 E0 0 0 0 0 0 1 1 1 1 1 E1 0 1 1 1 1 0 0 0 0 1 E2 1 0 0 1 1 0 0 1 1 0 E3 1 0 1 0 1 0 1 0 1 0
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4. EXCESS-3 TO BCD CODE CONVERTER:
TRUTH TABLE: Input Excess-3 code E8 E4 E2 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0
E1 1 0 1 0 1 0 1 0 1 0
B8 0 0 0 0 0 0 0 0 1 1
Output BCD Code B4 B2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0
B1 0 1 0 1 0 1 0 1 0 1
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PROCEDURE: 1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table.
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3. Check for the output as given in the characteristics table by the glowing of LED.
RESULT:
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EX. NO: 6
DATE: AIM:
DESIGN OF PARITY GENERATOR
To design and verify the operation of 16 bit odd / even parity checker generator using IC74180
APPARATUS REQUIRED: Sl.No. 1 2 3 THEORY: 16 BIT ODD/EVEN PARITY CHECKER/GENERATOR: IC74180 is a monolithic, 8 bit parity checker / generator which features control inputs and even/odd outputs to enhance operation in either odd or even parity applications. Cascading these circuits allows unlimited word length expansion. Typical application would be to generate and check parity on data being transmitted from one register to another.16 bit circuit could be designed by cascading two IC74180. TRUTH TABLE: COMPONENTS 8 bit odd/parity checker Digital Trainer Kit Digital Power Supply SPECIFICATION/R ANGE IC74180 (0 12) V (0 5) V Qty 2 1 1
L Logic low, H Logic High X Dont care
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36
PIN DESCRIPTION:
CIRCUIT DIAGRAM:
PIN DIAGRAM:
LOGICAL SYMBOL:
36
37
PROCEDURE:
1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table. 3. Check for the output as given in the characteristics table by the glowing of LED.
RESULT:
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Ex. No.7 Date: AIM:
To design and construct a combinational circuit for Encoder and Decoder using Logic Gates.
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DESIGN OF ENCODERS AND DECODERS
APPARATUS REQUIRED: S.No 1. 2. 3. 4. Components Require RPS Resistor LED ICS Range +5V 330 --7432 7408 7404 7421 Quantity 1 4 4 1 1 1 2
ENCODER THEORY An Encoder is a digital circuit that performs the inverse operation of a decoder An Encoder has 2n input lines and n output lines .The output lines generates the binary code corresponding to the input value The above circuit shows the operation of Priority Encoder .The priority Encoder is an Encoder Circuit that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to one at the same time, the input have the highest priority will take precedence In the truth table, the X s are dont care conditions that designate the fact that binary value may be equal to 1 or 0 Input D3 has the highest priority level; so regardless of the value of other inputs, when this input is 1,the output of xy is 11 (binary 3). D2 has the next priority level .The output is 10 (binary 2) if D2 is equal to 1, provided D3=0, regardless of the value of other two lower priority inputs .the output o for D1 is generated only if higher priority inputs are 0 and so on down the priority level. A valid output indicator, designated by Z is set to 1 only when one or more of the inputs are equal to 1 .If all the inputs are 0,Z is equal to 0, and the other two outputs of the circuits are not used
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PINDIAGRAM
39
CIRCUIT DIAGRAM:
D0
39
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X = D2 + D3 Y = D1D2 + D3 Z = D0 + D1+ D2 + D3
TRUTH TABLE:
D0 0 1 X X X
D1 0 0 1 X X
D2 0 0 0 1 X
D3 0 0 0 0 1
X X 0 0 1 1
Y X 0 1 0 1
Z 0 1 1 1 1
DECODER
THEORY Discrete quantities of information are represented in digital systems with binary codes. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n output lines
The decoder presented here is called 2 to 4 line decoder .The two inputs are decoded into 4 outputs, each output representing one of the minterms of the 2 input variables. The 2 inverters provide complement of the inputs, and each of the 4 AND gates generate one of the minterms
TRUTH TABLE:
A 0 0 1 1
B 0 1 0 1
D0 1 0 0 0
D1 0 1 0 0
D2 0 0 1 0
D3 0 0 0 1
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CIRCUIT DIAGRAM
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D0 = AB D1 = AB D2 = AB D3 = AB
PROCEDURE:
1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table. 3. Verification of glowing LED confirms the required data in the truth table. .
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RESULT:
QUESTIONS:
1. Realise 3 input AND gate and 3 input OR gate using 4x1 MUX and 2 input AND function using 2x1 MUX. 2. Realise a simple Boolean function of your choice using 4x1 MUX constructed by you. 3. What is Multiplexing? 4 What is the difference between Multiplexing and Demultiplexing? 5What are different types of Multiplexing techniques? 6. What is a Demultiplexer? 7. What is the difference between Demultipexer and Decoder? 8. How many select lines are needed to construct a 1x8 Demultipexer? Design it. 9. What is an Encoder?
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EX.NO :8 Date: AIM:
DESIGN OF SYNCHRONOUS COUNTERS (UP, DOWN, &BCD).
To design and construct the following synchronous counter and to verify its truth table.
APPARATUS REQUIRED:
SPECIFICATION/ RANGE IC7476 IC7408 IC7432 (0 12) V (0 5) V
Sl.No. 1 2 3 4 5
COMPONENTS JK FLIP-FLOP AND GATE OR GATE Digital Trainer Kit Digital Power Supply
Qty 2 1 1 1 1
PIN DIAGRAM OF IC7476
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3 BIT SYNCHRONOUS COUNTER

THEORY When a Counter is Clocked such that each Flip flop in the Counter is Triggered at
the same time ,the counter is called Synchronous counter QA changes on each clock pulse as we progress from its original state to its final stack and then back to its original state .In Synchronous binary counter, the flip-flop in the lowest order position is complemented with every pulse A flip-flop in any other position is complemented with a pulse provided all the bits in the lower order positions are equal to 1 . the binary count indicates that next higher order bit be complemented .Synchronous binary counters have a regular pattern and can be easily constructed with complementing flip-flops and gates .The counter could also be triggered on the positive edge of the pulse CIRCUIT DIAGRAM:
Q1 Q2 Q3
HIGH 1 2 J1 4 > 1 K1 16 FF1 K2 3 2 15 J2 9 7 11 FF2 J1 4 > 1 K1 16 FF3 2 15 3 PRESET +5V
>6
12
CP
CLEAR +5V
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TRUTH TABLE
45
CLK 0 1 2 3 4 5 6 7 8
Q3 0 0 0 0 1 1 1 1 0
Q2 0 0 1 1 0 0 1 1 0
Q1 0 1 0 1 0 1 0 1 0
SYNCHRONOUS DOWN COUNTER
BCD SYNCHRONOUS COUNTER

THEORY A BCD Synchronous counter counts in binary coded decimal from 0000 to 1001 and back to 0000. Because of return to 0 after count 9 ,BCD counter does not have a regular pattern as in a straight binary count .The excitation for T flip-flops is obtained from present and next states Synchronous BCD Counters can be cascaded to form a counter for Decimal numbers of any length
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46
CIRCUIT DIAGRAM
Q4 Q1 Q2 Q3 PRESET 12 HIGH 4 5 1 J1 4 > 1 K1 16 FF1 2 3 15 2 >6 K2 3 FF2 J2 9 7 11 4 >1 2 J1 15 FF1 6 13 9 10 11 1 2 8 J2 7 11 Q FF2 +5V 3
>6 K2
12
K1 16
12
10
Q'
CP
CLEAR +5V
TRUTH TABLE
CLK 0 1 2 3 4 5 6 7 8 9 10
Q4 0 0 0 0 0 0 0 0 1 1 0
Q3 0 0 0 0 1 1 1 1 0 0 0
Q2 0 0 1 1 0 0 1 1 0 0 0
Q1 0 1 0 1 0 1 0 1 0 1 0
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PROCEDURE:
1. The components are connected as shown in the circuit diagram. 2. The counter is set initially in the reset position. 3. Apply the clock pulse. It starts counting.
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4. Continue giving the clock pulse and check for the output as given in the truth table. 5. The output is indicated by the LED display. The glowing of LEDs confirming to required data in the truth table is verified and the conclusion is drawn.
RESULT:
QUESTIONS:
1. What is Ripple counter? 2. What are preset and clear lines? 3. What is the difference between Binary Ripple Counter and BCD Ripple Counter? 4. What is the difference between Synchronous Counter and Asynchronous Counter? 5. What is other name for Ripple Counter? 6. What are the Applications of Counters?
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EX. NO:9 DESIGN OF ASYNCHRONOUS COUNTERS (UP, DOWN, &BCD). Date: AIM:
To design and construct the following asynchronous counter and to verify its truth table.
APPARATUS REQUIRED:
SPECIFICATION/ RANGE IC7476 IC7408 IC7432 (0 12) V (0 5) V
Sl.No. 1 2 3 4 5
COMPONENTS JK FLIP-FLOP AND GATE OR GATE Digital Trainer Kit Digital Power Supply
Qty 2 1 1 1 1
PIN DIAGRAM OF IC7476
48
49
3 BIT RIPPLE UPCOUNTER

THEORY Three JK flip-flops are used with their inputs connected to Vcc. Negative Edge Triggering is used. The small circle in the CP input indicates that the flip-flop complements during a Negative going transition or when the output to which is connected goes from 1 to 0 .The flip-flop changes one at a time propagates through the counter in a ripple fashion .Ripple counter are called as Asynchronous Counter
CIRCUIT DIAGRAM
TRUTH TABLE
CLK 0 1 2 3 4 5 6 7 8 49
Q3 0 0 0 0 1 1 1 1 0
Q2 0 0 1 1 0 0 1 1 0
Q1 0 1 0 1 0 1 0 1 0
50
ASYNCHRONUS DOWN COUNTER:
TRUTH TABLE
CLK 8 7 6 5 4 3 2 1 0
Q3 0 1 1 1 1 0 0 0 0
Q2 0 1 1 0 0 1 1 0 0
Q1 0 1 0 1 0 1 0 1 0
PROCEDURE:
1.The components are connected as shown in the circuit diagram. 2.The counter is set initially in the reset position. 3.Apply the clock pulse. It starts counting. 4.Continue giving the clock pulse and check for the output as given in the truth table. 5.The output is indicated by the LED display. The glowing of LEDs confirming to required data in the truth table is verified and the conclusion is drawn.
50

RESULT:
51
QUESTIONS:
1.What is Ripple counter? 2.What are preset and clear lines? 3.What is the difference between Binary Ripple Counter and BCD Ripple Counter? 4.What is the difference between Synchronous Counter and Asynchronous Counter? 5.What is other name for Ripple Counter? 6.What are the Applications of Counters?
7.How many states does a modulus-14 counter has? 51 VIDYAA VIKAS COLLEGE OF ENGG & TECH

Ex. No: 10 Date: AIM:
To construct the following Shift Registers i.)Serial in Serial out Shift left Register Ii) Serial in Serial out Shift Right Register Iii) Serial in Parallel out IV) Parallel in Serial out V) Parallel in Parallel out Shift register
52
SHIFT REGISTERS (All Types)
APPARATUS REQUIRED:
SPECIFICATION/ RANGE IC7474 (0 12) V (0 5) V
Sl.No. 1 2 3
COMPONENTS D FLIP-FLOP Digital Trainer Kit Digital Power Supply
Qty 2 1 1
SERIAL-IN SERIAL OUT

THEORY Shift Register is very important in applications involving the storage and transfer of data in Digital Systems. The basic difference between a register and counter is that a register has no specified sequence of states. A register, in general is used for temporary storing and shifting data in Digital systems. This type of Shift Register enters data serially that is, one bit at a time on a single line .It produces the stored information on its output also in serial form.
52
53
CIRCUIT DIAGRAM - SERIAL IN SERIAL OUT SHIFT LEFT REGISTER
TRUTH TABLE
CLK 1 2 3 4
D3 0 0 0 1
D2 0 0 1 1
D1 0 1 1 1
D0 1 1 1 1
CIRCUIT DIAGRAM - SERIAL IN SERIAL OUT SHIFT RIGHT REGISTER
53
54
TRUTH TABLE
CLK 1 2 3 4
D0 1 1 1 1
D1 0 1 1 1
D2 0 0 1 1
D3 0 0 0 1
SERIAL-IN PARALLEL OUT

THEORY This type of Shift Register enters data serially that is, one bit at a time on a single line. Once the data are stored, each bit appears on its respective output line and all the bits are appeared simultaneously, rather than on a bit-by bit basis as with the serial output. CIRCUIT DIAGRAM
TRUTH TABLE
CLK 1 2 3 4 54
INPUT 1 1 1 1
D0 1 1 1 1
D1 0 1 1 1
D2 0 0 1 1
D3 0 0 0 1

PARALPARALLEL IN SERIAL OUT
THEORY
55
For a register with parallel data inputs, the bits are entered simultaneously into their respective stages on Parallel lines rather than on a bit-by-bit basis on one line as with Serial data inputs .The Serial output is executed once the data are completely stored in the Register
CIRCUIT DIAGRAM
SHIFT/ A LOAD 1 B 2
1
2 1
2 4
5 4
5 10
9 10
8 3 1 3 2 6 4 5 6 8 10 9
3 2 QA > 3 FF2 5 QA 12 QB > 9 QB
6 2 QC FF2 11 FF1 >3 FF2 5 QC
8 12 QD >11 FF1 9 QD SERIAL DATA OUT
CP
SHIFT/LOAD
1 0
ENABLED GATES
G4,G5,G6 G1.G2,G3
OPERATION
SHIFT DATA ENTRY
55
56
TRUTH TABLE
CP 1 2 3 4
SHIFT/ LOAD 0 1 1 1
A 1 1 1 1
B 0 1 1 1
C 1 0 1 1
D 0 1 0 1
SERIAL OUT 0 1 0 1
PIN DIAGRAM VCC 2Q' 2D 2CLK 2S' 2Q 2Q'
14
13 I C
12 7 3
1CLK
11 4 4
1S'
10 7 4 5
1Q
1
1R'
2
1D
6
1Q'
7
GND
PARALLEL IN PARALLEL OUT REGISTERS

THEORY The Parallel in Parallel out register employs both the methods : Immediately following the simultaneous entry of all data bits ,the bits appear on the parallel outputs TRUTH TABLE
CLK 1 2 3 4
ABCD 000 1 0011 0111 1111
QA 0 0 0 1
QB 0 0 1 1
QC 0 1 1 1
QD 1 1 1 1
56

CIRCUIT DIAGRAM
57
PROCEDURE:
1. The components are connected as shown in the circuit diagram. 2. The clock pulse is given and it is checked whether the bits shifts.
RESULT:
QUESTIONS:
1. Define a register. 2. Define a shift register. 3. What changes should be made in the circuit to roll the datas? 4 What is difference between Counter and Shift Register?
57

EX NO: 11 Date :
58
FOUR-BIT RING COUNTER
AIM: To study and construct a Four bit ring counter using Flip-Flops. APPARATUS REQUIRED:
S.NO 1 2
COMPONENTS IC 7474 DIGITAL TRAINER KIT
SPECIFICATION/RANGE -
QUANTITY 2
(0-12) V
CIRCUIT DIAGRAM:
TRUTH TABLE: CLK QA QB 0 0 1 2 1 0 3 0 1 4 1 1 5 0 0 6 1 0 7 0 1
QC 0 0 0 1 0 0 0
QD 0 0 0 0 1 1 0
58
59
PIN DIAGRAM
VCC R2' D2 CLK2 S2' Q2
Q2'
14 13 12 11 10 I 1 2 C 3 7 4 4 5 7 6
9 4 7
R1' D1 CLK1 S1' Q1
Q1' GND
PROCEDURE: 1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table. 3. Check for the output as given in the characteristics table
RESULT:
59
DIGITAL ELECTRONICS LAB Ex.No.12

Date: AIM:
60
MULTIPLEXERS AND DEMULTIPLEXER AND EXTENSIONS
To design and construct a combinational circuit for Multiplexer, Demultipexer, Encoder and Decoder using Logic gates.
APPARATUS REQUIRED:
Sl.No. 1 2 3 4 5 6 COMPONENTS OR GATE 3 INPUT AND GATE 2 INPUT AND GATE NOT GATE Digital Trainer Kit Digital Power Supply SPECIFICATION/ RANGE IC7432 IC7411 IC7408 IC7404 (0 12) V (0 5) V Qty 1 2 1 1 1 1
MULTIPLEXER
THEORY Multiplexing means transmitting a large number of information units over a smaller number of channels or lines A Digital Multiplexer is a combinational circuit that selects binary information from one of the many input lines and directs it to a single output line The selection of a particular input line is controlled by a set of selection lines Normally there are 2 n input lines and n selection lines whose bit combinations determine which input is selected A 4-to-1-line Multiplexer is shown in the fig. Each of the four input lines I0 to I3 is applied to one input of an AND gate Selection lines S1 and S0 are decoded to select a particular AND Gate Consider the case S1 S0=10 .the AND Gate associated with input I2 has two of its inputs equal to 1 and third input connected to I2 he other three AND Gates have at least one input equal to 0, which makes their outputs equal to 0 The OR Gate output is now equal to the value of I2, thus providing a path from the selected input to to the output
60
61
A Multiplexer is also called Data Selector, since it selects one of many inputs and steers the binary information to the output line
CIRCUIT DIAGRAM
TRUTH TABLE: Data Input Select Line S1 S0 Output
( X- Dont care) I0=X I1=X I2=X I3=X
0 0 1 1
0 1 0 1
I0=X I1=X I2=X I3=X
61

PINDIAGRAM
62
DEMULTIPLEXER:
THEORY A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2 n possible output line A decoder with an Enable input can function as a Demuxtiplexer The selection of a specific output line is controlled by a bit value of n selection lines.
62
63
The Decoder can function as a Demuxtiplexer if I line is taken as a data input line and lines S1 and S0 are taken as a selection lines.
The single input variable I have a path to all 4 outputs, but the input information is directed to only one of the output lines, as specified by the binary values of the two-selection linesS1 and S0.
CIRCUIT DIAGRAM:
63

TRUTH TABLE Data Input (I) Select Line S1 S0 Output
64
( X- Dont care) X X X X
0 0 1 1
0 1 0 1
D0=X D1=X D2=X D3=X
PROCEDURE:
1. Connect the components as per the given circuit. 2. Apply the bits as per the truth table. 3. Verification of glowing LED confirms the required data in the truth table.
RESULT:
64
65
EX. NO: 13 DATE: AIM:
DESIGN OF 4 BIT ADDERS / SUBTRACTORS
To design and verify the operations of 4-bit binary adder/Subtractor and BCD adder using IC 7483. APPARATUS REQUIRED: SPECIFICATION/ RANGE 4 BIT BINARY ADDER IC7483A EXOR, 3 Input AND, NAND IC7486, IC7411, GATE IC7400 Digital Trainer Kit (0 12) V Digital Power Supply (0 5) V
Sl.No. COMPONENTS 1 2 3 4
Qty 1 1 1 1
THEORY: The 7483A high speed 4 bit binary full adders with internal carry look ahead accept two 4 bit binary words A0 A3 & B0 B3 and a carry input, C0. They generate the binary sum outputs, S0 S3 and a carry output, C4.
The circuit adds the two 4 bit binary words (A and B) plus the incoming carry. The binary sum appears on the sum outputs (S0 S3) and outgoing carry (C4) output. C0 + (A0 + B0) + 2(A1 + B1) + 4(A2 + B2) + 8(A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4
65
66
PIN DIAGRAM
LOGICAL SYMBOL
CIRCUIT DIAGRAM: 4 BIT ADDER:
66
67
TRUTH TABLE:
4 BIT ADDER / SUBTRACTOR:
TRUTH TABLE: A 3 0 1 1 1 A Input A A 2 1 0 0 0 0 0 0 0 0 A 0 1 1 1 1 B 3 0 0 0 1 B Input B B 2 1 1 1 1 1 1 1 0 1 Mode Input B 0 1 1 1 0 M 0 0 1 1 (Addition) (Subtraction) S 3 1 0 0 1 Sum S2 0 0 0 1 S1 0 0 1 1 S0 0 0 0 1 Carry Cout 0 1 0 1
67

BCD ADDER:
68
RESULT:
68

Ex:NO:14 DATE: AIM: To implement the circuit with a PAL , PLA And ROM memories MEMORIES
69
APPARATUS REQUIRED:
Sl.No. 1 2 3 4 5 COMPONENTS AND Gate OR Gate NOT Gate Digital IC Trainer Digital Power Supply SPECIFICATION/ RANGE IC7408 IC7432 IC7404 IC 7486 IC 7400 Qty 10 3 4 1 1
PLA-Progammable Logic Array Aim: To implement the circuit with a PLA having 3 inputs, 3 product terms and 2 outputs with the function of F1=m(3,5,7), F2=m(4,5,7). TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F1 0 0 0 1 0 1 0 1 F2 0 0 0 0 1 1 0 1
69

PLA Program Table: Protuct Term 1 2 3
70
A 1 1
Inputs B 1 0
Outputs C 1 1 F1 1 1 T F2 1 1 T
CIRCUIT DIAGRAM:
70

PAL-Progammable Array Logic AIM: To implement the circuit using PAL CIRCUIT DIAGRAM
71
71

TRUTH TABLE: A 0 1 2 3 4 5 0 0 0 0 0 0 B 0 0 0 0 1 1 C 0 0 1 1 0 0 D 0 1 0 1 0 1 W 1 0 1 0 0 0 X 1 0 1 0 0 0 Y 0 0 1 1 0 0 Z 0 1 0 1 1
72
6 7 8 9 10
0 0 1 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1
1 1 1 1 0 0 1 1 0 0
1 1 1 1 0 0 1 1 1 0
0 0 1 1 1 0 1 1 0 0
1 0 0
1 0 0 1 0 1 0
11 12 13 14 15
72
73
ROM-Memories: AIM: To implement the following Boolean function using ROM. F1(A1,A0)=m(1,2) F2(A1,A0)= m(0,1,3) ROM MEMORIES
RESULT
73
74
74

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VIDYAA VIKAS COLLEGE OF ENGG & TECH