CMOS Inverter Power

Dissipation
Why worry about power? -- Power
Dissipation
P6
Pentium
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
P
o
w
e
r

(
W
a
t
t
s
)
Lead microprocessors power continues to increase
Lead microprocessors power continues to increase
Power delivery and dissipation will be prohibitive
Power delivery and dissipation will be prohibitive
Source: Borkar, De Intel
Why worry about power? -- Chip
Power Density
4004
8008
8080
8085
8086
286
386
486
Pentium
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P
o
w
e
r

D
e
n
s
i
t
y

(
W
/
c
m
2
)
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Suns
Surface
chips might become hot
Source: Borkar, De Intel
CMOS inverter power
Power has three components
Static power: when input isnt switching
Dynamic capacitive power: due to charging and
discharging of load capacitance
Dynamic short-circuit power: direct current
from V
DD
to G
nd
when both transistors are on
CMOS inverter static power
Static power consumption:
Static current: in CMOS there is no static current as long as V
in
<
V
TN
or V
in
> V
DD
+V
TP
Leakage current: determined by off transistor
Influenced by transistor width, supply voltage, transistor threshold
voltages
V
DD
V
I
<V
TN
I
leak,n
Vcc
V
DD
I
leak,p
Vo(low)
V
DD
Leakage (Static) Power Consumption
Sub-threshold current is the dominant factor.
All increase exponentially with temperature!
V
DD
I
leakage
Vout
Drain junction
leakage
Sub-threshold current
Gate leakage
Dynamic Power Consumption
Vin Vout
C
L
Vdd
Dynamic Capacitive Power and energy stored in the
PMOS device
Case I: When the input is at logic 0: Under this
condition the PMOS is conducting and NMOS is in
cutoff mode and the load capacitor must be
charged through the PMOS device.
Power dissipation in the PMOS transistor is given by,
P
P
=i
L
V
SD
= i
L
(V
DD
-V
O
)
The current and output voltages are related by,
i
L
=C
L
dv
O
/dt
Similarly the energy dissipation in the PMOS device
can be written as the output switches from low to
high ,
Above equation showed the energy stored in the
capacitor C
L
when the output is high.
2
2
0
2
0
0 0 0 0
2
1
) 0
2
( ) 0 ( ,
2
, ) (
DD L P
DD
L DD DD L P
V
O
L
V
O DD L P
O
V
O L
V
O DD L P
O
O DD L P P
V C E
V
C V V C E C V C E
d C d V C E dt
dt
d
V C dt P E
DD
DD
DD DD
=
= =
= = =
} } } }

v
v
v v v
v
v
Power Dissipation and Total Energy Stored in the
CMOS Device
Case II: when the input is high and out put is
low:
During switching all the energy stored in the load
capacitor is dissipated in the NMOS device
because NMOS is conducting and PMOS is in
cutoff mode. The energy dissipated in the NMOS
inverter can be written as,
The total energy dissipated during one switching
cycle is,
The power dissipated in terms of frequency can be
written as
2
2
1
DD L N
V C E =
2 2 2
2
1
2
1
DD L DD L DD L N P T
V C V C V C E E E = + = + =
2
DD
L T
T
T
V fC fE P
t
E
P t P E = = =
This implied that the power dissipation in the CMOS inverter is directly
proportional to switching frequency and V
DD
2
Dynamic capacitive power
Formula for dynamic power:
Observations
Does not (directly) depend on device sizes
Does not depend on switching delay
Applies to general CMOS gate in which:
Switched capacitances are lumped into C
L
Output swings from Gnd to V
DD
Input signal approximated as step function
Gate switches with frequency f
f V C P
DD L dyn
2
=
Not a function of transistor sizes!
Data dependent - a function of switching activity!
Lowering Dynamic Power
P
dyn
= C
L
V
DD
2
f
Capacit ance:
Funct ion of fan-out ,
wire lengt h, t ransist or
sizes
Supply Volt age:
Has been dropping
wit h successive
generat ions
Clock frequency:
I ncreasing
Short Circuit Power Consumption
Finite slope of the input signal causes a direct
current path between V
DD
and GND for a short
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Vin Vout
C
L
I
sc
Dynamic short-circuit power
Short-circuit current flows from V
DD
to Gnd when both transistors are
on
Plot on VTC curve:
V
CC
V
CC
V
in
V
out
I
D
I
max
I
max
: depends on
saturation current
of devices
Dynamic short-circuit power
Approximate short-circuit current as a triangular wave
Energy per cycle:
f I V
t t
P
I V
t t t I
V
t I
V E
CC
f r
sc
CC
f r f
CC
r
CC sc
max
max
max
max
2
2 2 2
+
=
+
= + =
I
max
Short Circuit Currents Determinates
Duration and slope of the input signal, t
sc
I
peak
determined by
the saturation current of the P and N transistors which
depend on their sizes, process technology, temperature,
etc.
strong function of the ratio between input and output
slopes
a function of C
L
P
sc
= t
sc
V
DD
I
peak
f
01
Impact of C
L
on P
sc
Vin Vout
C
L
I
sc
~

0
Vin Vout
C
L
I
sc
~

I
max
Large capacitive load
Output fall time significantly
larger than input rise time.
Small capacitive load
Output fall time substantially
smaller than the input rise
time.
I
peak
as a Function of C
L
-0.5
0
0.5
1
1.5
2
2.5
0 2 4 6
I
p
e
a
k
(
A
)
time (sec)
x 10
-10
x 10
-4
C
L
= 20 fF
C
L
= 100 fF
C
L
= 500 fF
500 psec input slope
Short circuit dissipation
is minimized by
matching the rise/fall
times of the input and
output signals - slope
engineering.
When load capacitance
is small, I
peak
is large.
Inverter power consumption
Total power consumption
leak CC
f r
CC CC L tot
stat sc dyn tot
I V f
t t
I V f V C P
P P P P
+
|
|
.
|

\
|
+
+ =
+ + =
2
max
2
Power reduction
Reducing dynamic capacitive power:
Lower the voltage (Vdd)!
Quadratic effect on dynamic power
Reduce capacitance
Short interconnect lengths
Drive small gate load (small gates, small fan-out)
Reduce frequency
Lower clock frequency -
Lower signal activity
f V C P
DD L dyn
2
=
Examples
f=500MHz
C
L
=15fF/gate
V
DD
=2.5V
P
dyn
=50W
For a design with I million gate
P
dyn
=50W!
Is this possible in reality? If not why?
P
dyn
=E
dyn
/2t
p
=580W for t
p
=32.5ps
P
dyn
=E
dyn
/2t
p
=155W for f=4GHz(250ps)
Power reduction
Reducing short-circuit current:
Fast rise/fall times on input signal
Reduce input capacitance
Insert small buffers to clean up slow input
signals before sending to large gate
Reducing leakage current:
Small transistors (leakage proportional to
width)
Lower voltage
Retrospect on Design Trade-offs
Design trade-offs dance
around the triangle, but
still important
Fundamental improvement
that shrinks the triangle:
Scaling in technology
(lithography
improvement)
New functionality
New architecture
New algorithms
Good
Fast Cheap
(Lower-power and Robust)
(Short Delay) (Small Layout)