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Digital Systems Design - 2
Digital Systems Design - 2
REPORT + design + “.rpt” report_constraint >> REPORT + design + “.rpt” report_area >> REPORT + design + “.rpt” report_timing >> REPORT + design + “.rpt” create_schematic -all write -£ db ~hier -o DBDIR + design + “.db" remove_design -design xemove_License VEDL-Compiler Figure 3-13 File compile.report. In Design Analyzer, the command “include compile.pargen” can be run. Fig- ure 3-14 shows the synthesized schematic, Directory ../db has a file pargen.db. Directory ../report has a file pargen.rpt. It is strongly recommended that ../rtl- sim.work and ./syn.work be separate directories. When both Synopsys VHDL simu- lation and synthesis tools use the same working library, if the time stamp of a file is changed by one tool this would cause the problem of “out of date” issue for the other tool. Separating the two directories reduces the impact between the VHDL simulation process and the synthesis process. Note that all design directories are retatively specified, This reduces the changes required when the design directory is moved (copied) into another location. Establish- ing a common directory structure (for the same project, design group, company) enables designers to find things much more easily. It also allows designers to support various projects without feeling things are out of place. However, setting up an agreed directory structure is Sometimes a very personat matter. Guidelines should be estab- lished and disciplines should be maintained for the project supported by multiple designers.Chapter3 VHDL Simulation and Synthesis Environment and Design Process PAR Figure 3-14 Synthesized schematic for PARGEN.3.4 Synthesis Technology Library 45 3.4 SYNTHESIS TECHNOLOGY LIBRARY A synthesis technology library consists of definitions of basic components, operating conditions, and wire load models. Basic components are selected by the synthesis tool to implement the VHDL design based on functions, timing, area, and synthesis con- straints. Each component has its logical function, timing, input pin loading, and out- put pin drive information. The library is usually provided by the ASIC or FPGA. manufactures in a binary format understood by Synopsys synthesis tools. The synthe- sis technology library usually comes as library_name.db. The associated symba? library is usually named library_name.sdb, For example, the synopsys_de.setup file discussed above specifies 1ca300k.db and 1ca300k.sdb, which are stored in direc- tory, /acct/synlib/isi. Inside the Design Analyzer, command “read /acct/syntiby/Isi/ 1ca300K.db” can be used to read in the synthesis technology library. Command report_lib Iea300k can be used to report the library. The following shows part of the report. Lines 1 to 5 specify units used in the library. Lines 7 to 17 define several oper- ating conditions. For example, operating condition WCMIL (worst case military) is 125 degrees with 4.5 volts. The derating factor is 1.4, which is 40 percent slower than the nominal operating condition at 25 degrees with 5.0 volts. Lines 19 to 36 declare a wire load model. Lines 27 to 36 are a lookup table. Each entry specifies the estimated wire length for a fanout number (the number of input pins connected to an output pin of a component). The wire length is then converted to a resistance and capacitance value to calculate the timing delay. Line 26 is the slope value which is used to calcu- late the wire length when the fanout is larger thaa the largest fanout number in the table. Time Unit + Ins Capacitive Load unit + 1,000000pE Pulling Resistance Unit : 1kilo-ohm Voltage unit w : Ima Operating Conditions: 1 z 3 4 5 Current unit 6 7 8 Name Process Temp Volt —Interconnect Model. oo 10 NOM 2.00 25.00 5.00 —_best_case_tree 11 WCCOM 1.40 70.00 4.75 Worst_case_tree 12 WCIND 1.40 85.00 4.75 worst_case_tree 13° WML 1.40 125.00 4.50 worst_case_tree 14 BCCOM 0.70 «0.00 5.25 best_case_tree 15 BCIND 0.70 -40.00 5.25 best_case_tree 16 BOMIL 9.70 -55.00 5.50 best_case_tree 17° TST 1.40 25.00 5.00 —bast_case_tree 18 19 Name BBXX * 20 Location Lice 21 Resistance —:_—«0-020929 22 Capacitance 0.14221 23° Area + 8.28598Chapter3_ VHDL Simulation and Synthesis Environment and Design Process 24 Slope + 0.398 25 Fanout Length Points Average Cap Std Deviation 26 - 27 1 0.40 28 a 0-80 29 3 1.19 30 4 1.59 31 5 1.99 32 6 2.39 33 7 2.79 34 8 3.18 35 9 3.58 36 10 3.98 ‘The following table shows a summary of five actual synthesis libraries. The table gives a quick summary about the library. The bigger the number is in each col- umn, the greater the likelihood that the library is more calibrated. If the library has only one wire load model as shown in Library E, call the manufacture and ask when the wire load model should be used. If the answer is either “do not know” or “10 mils block,” purge the synthesis library and save the disk space, and avoid the grief from a design that did not work. Number of Number of wire load | Maximum number of operating conditions | models fanout in the wire foad model Library A 8 62 10 Library B 14 40 99 Library C 6 4 24 Library D 3 7 40 Library E 3 1 5 Figure 3-15 Synthesis libraries summary. It is important to select a good synthesis library (and manufacturer) to match your design objectives. For example, speed requirements, cost, production schedule, and design tools are all factors that need to be considered. Assume that a synthesis library has been selected. Find out the following Use the report_lib command to list the component names in the library. Are input/output (VO) pads included in the library? Some manufacturers provide I/O pads in a separate library. Check whether the three-state output pads and bidirectional pads enable input is low or high active (also use the data book). In general, I/O pads are instantiated with component instantiation, By providing the enable signal at the right level with synthesis, the signal can then be used directly in the I/O pad component instantiations.3.5 VHDL Design Process for A Block 47 + Are there clock buffer components? How is the clock buffer (or clock buffer tree) implemented? Is it inserted i the place / route process? + Are there delay components? The design may need to use a delay component. + How many different types of flip-flops? Are there any scan flip-flops? Are reset and present synchronous or asynchronous? + Ask the vendor whether he has a recommended common synthesis script to set up before synthesizing any block. For example, a vendor suggests the following commands to set the maximum capacitance and maximum transition in line 1 and 4, Line 2 sets the input to port to have the same drive as an inv_1x output drive. Line 3 sets up all output ports to Grive the input pin IN1 of an inv_3x component. Note that component names inv_ix and inv_3x are used which can be found by the report_lib command, 1 set_max_capacitance get_attribute(hx2000_we/inv_1x/ OuT1,max_capacitance) all_inputs() 2 set_driving cell -cell inv_1x all_inputs() 3 set_load get_attribute(hx2000_we/inv_3x/IN1,capacitance) all_outputs() 4 set_max transition get_attribute(hx2000_we/inv_1x/ TW1,max_transition) all_outputs() + Prepare files .synopsys_dc.setup and compile.common. Bring up design_analyzer. Try a simple synthesis to ensure that .synopsys_dc.setup and compile.common arc executed correctly. Now we are ready to go. 3.5 VHDL DESIGN PROCESS FOR A BLOCK Now, we know how 10 write VHDL. We have set up the design directory structure, mapped VHDL libraries, and established synthesis libraries. We are anxious to start the design. Assume that we have blocks partitioned and are ready to design the first block. The question is when to do the VHDL simulation and when to do the synthesis. Do we wait until all blocks are designed with VHDL, and the whole desiga is verified before any synthesis is attempted? The answer is “no” for the following reasons: + The synthesis process can catch obvious design errors that are harder and slower to find with VHDL simulation. + If the design (schematic) is not close to what was intended, itis pointless to run the VHDL simulation. + It may take too much time to get all related blocks designed before a meaningful VHDL. simulation can be run, + The synthesis result may demand design changes. For example, a long path may need to be broken down to two clock cycles. The associated control signals need to be changed. For example, the following VHDL. code has passed the VHDL. syntax error check by running VHDL analyzer (Synopsys vhdlan or Mentor QuickVHDL qvcom).Chapter3_ VHDL Simulation and Synthesis Environment and Design Process ‘It may take some time to verify this block, not to mention to set up the test bench or to enter simulation commands. 37 38 Library IEEE; use TEEE.std_logic_1164.all; entity WRONG is port ( RStm, CLK in std_logic; A, B, C, D, E, F, G, Ht in std logic; FFL, FF2 + out std_logic; x, ¥, 2 + out std logic); end WRONG; architecture RTL of WRONG is signal EN1, EN2 : std_logic; begin PO : process (A, B, C, D, E, E, G, H) begin if (A= '0') or (B= ‘I') then X <= D nor (E nor F); elsif (C = /1’) then Y <= 6 xor Hy end if; end process; pl + process (RSTn, CLK) begin if (RSTn = /1') then ENL <= ‘0°; ny ny elsif (CLK’event and CLK = ‘1') then if (EN2 = '1') then FF2 <= A nor not B; end if; end if; end process; end RTL; The design can be read in the Design Analyzer with the command “read -f vhdl ../vhdl/ch3/wrong.vhd.” The following is a summary of the message. Lines 3 to 6 indi- cate that signal F is used in the process, but not in the sensitivity list. This is just a typo that shows two ‘E’s instead of one ‘EB’ and one ‘F’ in line 13. It will take many simula- tions before this error is discovered.3.5 VHDL Design Process for A Block “9 Reading in the Synopsys vhdl primitives. vhdl /ch3 /wrong.vhd: Warning: Variable ‘F’ is being read in routine WRONG line 13 in file ‘../vhdl/ch3/wrong.vhd’, but is not in the process sensitivity list of the block which begins there. (HDL-179) Inferred memory devices in process ‘pO’ in routine WRONG line 13 in file +. /whd1/ch3/wrong.vhd’ [Register Name| Type |Width| Bus | AR | AS | sR | ss | ST | | Latch | 1 | | patch | 2 | reset/set: none reset/set: none Inferred memory devices in process ‘pl’ in routine WRONG line 21 in file ‘.«/vhd1/ch3 /wrong.vha’ « [Register Name| Type |Width|Bus| AR | AS | SR | ss | sT | |EN1_reg |Flip-flop| 1 [-|¥ [uN |[N [NIN [| |EN2_reg |Flip-flop| 1 |-[N [wn [nN [Nn [mw | |FF1_reg JFlip-flop| 1 |-|N |¥ |N [Nn [wn] |FE2_xeg |Flip-flop] 1 |-[N |¥ |N |N (wf ENI_reg —- Async-reset: RSTn EN2_reg set/reset/toggle: none FF1_reg Async-set: RSTn FF2_reg Async-set: RSTn Warning: In design ‘WRONG’, port ‘2’ is not connected to any nets. (LINT-28) Lines 8 to 18 indicate that two latches are inferred in process pO that are not intended. This is caused by the incomplete assigning of a target object in an if or case statement. Lines 21 to 35 summarize the flip-flops. Note that EN2_reg is reported not asynchronously reset ot preset in lines 27 and 33. This may be just a miss. Lines 37 and 38 is a message from the check_design command after the VHDL code is read in. Output port Z is not used. Up to this point, the design has not even been synthesized. It is just read in and checked. These are common mistakes that can be found much more easily with the synthesis tool. The following VHDL code shows that the above errors have been corrected. Line 9 is replaced with line 10 to remove output port Z. Line 15 is replaced with line 16 to include F in the sensitivity list. Line 18 is added to set default values so that signals X and Y are completely assigned in every execution path, and the latches are not inferred. Line 29 is added to reset signal EN2.50 Chapter 3 VHDL Simulation and Synthesis Environment and Design Process i ~ file wrong2right.vhd 2 Library IEEE; 3 use IBEE.std logic_1164.al1; 4 entity WRONG is 5 port ( 6 STA, CLK in std_logic; 7 A, B, C, Dy By Fy G, Ht in std logic; 8 FF1, FF2 out std_logic; 9 —-X, ¥, 2 out std_logic); -- remove 2 10 x, ¥ 1 out std_logic); 11 end WRONG; 12 architecture RTL of WRONG is 13 signal EN1, EN2 : std_logic; 14 begin 15 --p0 + process (A, B, C, D, E, E, G, H) ~~ typo B-> F 16 pO = process (A, B, C, D, B, F, G, H) 17 begin 18 X <= 10"; ¥ <= ‘0; -- set value to remove latches 19 if (A= '0') or (B= ‘1') then 20 X <= D nor (E nor F); 21 elsif (C = ‘1’) then 22 ¥ <= G xor 8; 23 end if; 24 end process; 25 pl: process (RST, CLK) 26 begin 27 if (RSTn = ‘1') then 28 ENL <= '0'; 29 EN2 <= ‘0’; -- added EN2 30 FEL <= ‘1; 31 FF2 <= ‘1; 32 elsif (CLK’event and CLK = ‘1’) then 33 E nand F; 34 Anor H; 35 “Ly then 36 B and D; 37 38 *1") then 39 A nor not B; 40 end if; a end if; 42 end process; 43 end RIL; ‘The following is a summary message after the corrected VHDL file is read in. Note that only flip-flops (no latches) are inferred with asynchronous reset and set. Fig- ure 3-16 shows the synthesized schematic, Note that the asynchronous reset and set pins of the four flip-flops are connected to an inverter output of the RSTn input. This is due to line 27, which checks RSTn = ‘1’. This may be intended for RSTn = ‘0’. Lines 16 to 19 do not tell which way. It is a good practice to review the synthesized schematic to get a quick sense of obvious mistakes.3.5 VHDL Design Process for A Block 51 Reading in the Synopsys vhdl primitives. + +/whdl/ch3/wrong2right.vhd: Inferred memory devices in process ‘pl’ in routine WRONG line 24 in file + ../vhdl /ch3 /wrong2right .vhd' . |Width|pus| aR | AS | SR | SS | ST J [Register Name| }ENI_reg |Flip-flop| x [win | |EN2_reg |FLip-flop| vinx in | |FP1_reg |Flip-flop| oe |FLip-£lop| viwin |] Asyne-reset: RSTn Async-reset: RSTn Async-set: RSTn Async-set: RSTn Figure 3-16 Synthesized schematic for wrong2correct.vhd.52 Chapter3 VHDL Simulation and Synthesis Environment and Design Process 3.6 EXERCISES 3.1 Find how the $SYNOPSYS and SARCH environment variables are set by using Unix commands echo $SYNOPSYS and echo $ARCH. They are usually set in the .cshre (C Shell) file or .kshrc (Korn Shell) file. If they are not set, ask your system administrator how to set them up. Visit the SYNOPSYS directory to find out how subdirectories are set up. How many files are in $SYNOPSYS/packages/IEEE/stc directory? View each file and ‘write down the file name and its purpose. Use Unix command echo $PATH to see how the $PATH environment variable is set. Which directory contains the command: vhdlsim, vhdlan, vhdldbx, design_analyzer, de_shell? 3.2. Define a design directory structure for a design for which you alone are responsible. State your assumptions, guidelines, usages, advantages, and purposes. 3.3. Define a design directory structure for a design by two or more designers. State your assumptions, guidelines, usages, advantages, and purposes. 3.4 The directory structure shown in this chapter is more or less flat. Is this an advantage compared to a deeper directory structure? For example, directory rtlsim.work can be embedded inside directory rtlsim, 3.5 In Synopsys VHDL. simulation environment, how is the VHDL simulation library mapped? What are the advantages and disadvantages to share the working library for Synopsys VHDL simulation and synthesis tools? 3.6 In Mentor QuickVHDL (or Modelsim) simul simulation library mapped? 3.7, What isa VHDL primary design unit? What is a VHDL secondary design unit? 3.8 Use Synopsys Design Analyzer to read in a synthesis library. Determine the number of operating conditions, the number of wire load models, the largest fanout number in the wire load model table in the library. Are there any V/O pads, three-state buffers, clock ‘buffers, and delay components? 3.9 Prepare a synopsys_de.setup file and a compile.common file for your design. State your assumptions and verify that these two files can be executed correctly. 3.10 In this chapter, sample .synopsys_desetup, compile.common, compile.pargen, and compile.report files are presented. Discuss the advantages of these setups. Suggest improvements and state your reasons. 3.11 The mistakes made in the wrong.vhd ate very easy to make. If you do not have the synthesis tools, how do you find those errors with VHDL simulation tools? Estimate how Jong it will take and compare that with just a couple of minutes using synthesis tools. 3.12 What are some other mistakes that can be easily caught by using synthesis tools? 3.13 Refer to the wrong.vhd example. What would you do to avoid or minimize the same mistakes when you write VHDL code? environment, how is the VHDL