;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; ;;; msp430g2553 include file ;;; ;;; hacked from the msp430-gcc header file with

a series of regex replaces ;;; and a little bit of hand tweaking. ;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; ;;; STANDARD BITS ;;; BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BITA BITB BITC BITD BITE BITF equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000

;;; ;;; STATUS REGISTER BITS ;;; C Z N V GIE CPUOFF OSCOFF SCG0 SCG1 equ equ equ equ equ equ equ equ equ 0x0001 0x0002 0x0004 0x0100 0x0008 0x0010 0x0020 0x0040 0x0080

;;; ;;; Low Power Modes coded with Bits 4-7 in SR ;;; LPM0 LPM1 LPM2 LPM3 LPM4 equ equ equ equ equ CPUOFF SCG0+CPUOFF SCG1+CPUOFF SCG1+SCG0+CPUOFF SCG1+SCG0+OSCOFF+CPUOFF

;;; ;;; SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS ;;;

IE1 WDTIE OFIE NMIIE ACCVIE e IFG1 WDTIFG OFIFG PORIFG RSTIFG NMIIFG IE2 UC0IE UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE IFG2 UC0IFG UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG ;;; ;;; ADC10 ;;;

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ

0x0000 0x01 0x02 0x10 0x20 0x0002 0x01 0x02 0x04 0x08 0x10 0x0001 IE2 0x01 0x02 0x04 0x08 0x0003 IFG2 0x01 0x02 0x04 0x08

; Interrupt Enable 1 ; ; ; ; Watchdog Interrupt Enable Osc. Fault Interrupt Enable NMI Interrupt Enable Flash Access Violation Interrupt Enabl

; Interrupt Flag 1 ; ; ; ; ; Watchdog Interrupt Flag Osc. Fault Interrupt Flag Power On Interrupt Flag Reset Interrupt Flag NMI Interrupt Flag

; Interrupt Enable 2

; Interrupt Flag 2

#define __MSP430_HAS_ADC10__ lable ADC10DTC0 ADC10DTC1 ADC10AE0 ADC10CTL0 ADC10CTL1 ADC10MEM ADC10SA ; ADC10CTL0 ADC10SC ENC ADC10IFG ADC10IE ADC10ON REFON REF2_5V MSC REFBURST REFOUT ADC10SR ps ADC10SHT0 equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ 0x0048 0x0049 0x004A 0x01B0 0x01B2 0x01B4 0x01BC 0x001 0x002 0x004 0x008 0x010 0x020 0x040 0x080 0x100 0x200 0x400 0x800

; Definition to show that Module is avai ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 Data Transfer Data Transfer Analog Enable Control 0 Control 1 Memory Data Transfer Control 0 Control 1 0

Start Address

Start Conversion Enable Conversion Interrupt Flag Interrupt Enalbe On/Enable Reference on Ref 0:1.5V / 1:2.5V Multiple SampleConversion Reference Burst Mode Enalbe output of Ref. Sampling Rate 0:200ksps / 1:50ks

; ADC10 Sample Hold Select Bit: 0

ADC10SHT1 SREF0 SREF1 SREF2 ADC10SHT_0 ADC10SHT_1 ADC10SHT_2 ADC10SHT_3 SREF_0 SREF_1 SREF_2 SREF_3 SREF_4 SREF_5 SREF_6 SREF_7 ; ADC10CTL1 ADC10BUSY CONSEQ0 CONSEQ1 ADC10SSEL0 ADC10SSEL1 ADC10DIV0 ADC10DIV1 ADC10DIV2 ISSH ADC10DF ement SHS0 SHS1 INCH0 INCH1 INCH2 INCH3 CONSEQ_0 CONSEQ_1 CONSEQ_2 CONSEQ_3 ADC10SSEL_0 ADC10SSEL_1 ADC10SSEL_2 ADC10SSEL_3 ADC10DIV_0 ADC10DIV_1 ADC10DIV_2 ADC10DIV_3 ADC10DIV_4 ADC10DIV_5 ADC10DIV_6 ADC10DIV_7 SHS_0 SHS_1 SHS_2 SHS_3

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ

0x1000 0x2000 0x4000 0x8000 0x0000 0x0800 0x1000 0x1800 0x0000 0x2000 0x4000 0x6000 0x8000 0xA000 0xC000 0xE000 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000 0x0000 0x0002 0x0004 0x0006 0x0000 0x0008 0x0010 0x0018 0x0000 0x0020 0x0040 0x0060 0x0080 0x00A0 0x00C0 0x00E0 0x0000 0x0400 0x0800 0x0C00

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

ADC10 Sample Hold Select Bit: 1 ADC10 Reference Select Bit: 0 ADC10 Reference Select Bit: 1 ADC10 Reference Select Bit: 2 4 x ADC10CLKs 8 x ADC10CLKs 16 x ADC10CLKs 64 x ADC10CLKs VR+ VR+ VR+ VR+ VR+ VR+ VR+ VR+ = = = = = = = = AVCC and VR- = AVSS VREF+ and VR- = AVSS VEREF+ and VR- = AVSS VEREF+ and VR- = AVSS AVCC and VR- = VREF-/VEREFVREF+ and VR- = VREF-/VEREFVEREF+ and VR- = VREF-/VEREFVEREF+ and VR- = VREF-/VEREFBUSY Conversion Sequence Select 0 Conversion Sequence Select 1 Clock Source Select Bit: 0 Clock Source Select Bit: 1 Clock Divider Select Bit: 0 Clock Divider Select Bit: 1 Clock Divider Select Bit: 2 Invert Sample Hold Signal Data Format 0:binary 1:2's compl Sample/Hold Source Bit: 0 Sample/Hold Source Bit: 1 Input Channel Select Bit: Input Channel Select Bit: Input Channel Select Bit: Input Channel Select Bit:

ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10

0 1 2 3

Single channel single conversion Sequence of channels Repeat single channel Repeat sequence of channels ADC10OSC ACLK MCLK SMCLK ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 ADC10 Clock Clock Clock Clock Clock Clock Clock Clock Divider Divider Divider Divider Divider Divider Divider Divider Select Select Select Select Select Select Select Select 0 1 2 3 4 5 6 7

ADC10SC TA3 OUT1 TA3 OUT0 TA3 OUT2

INCH_0 INCH_1 INCH_2 INCH_3 INCH_4 INCH_5 INCH_6 INCH_7 INCH_8 INCH_9 INCH_10 INCH_11 INCH_12 INCH_13 INCH_14 INCH_15 ; ADC10DTC0 ADC10FETCH ADC10B1 ADC10CT ADC10TB ADC10DISABLE

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ

0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xA000 0xB000 0xC000 0xD000 0xE000 0xF000 0x001 0x002 0x004 0x008 0x000

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

Selects Selects Selects Selects Selects Selects Selects Selects Selects Selects Selects Selects Selects Selects Selects Selects

Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

This bit should normally be reset ADC10 block one ADC10 continuous transfer ADC10 two-block mode ADC10DTC1

;;; ;;; Basic Clock Module ;;; #define __MSP430_HAS_BC2__ lable DCOCTL BCSCTL1 BCSCTL2 BCSCTL3 MOD0 MOD1 MOD2 MOD3 MOD4 DCO0 DCO1 DCO2 RSEL0 RSEL1 RSEL2 RSEL3 DIVA0 DIVA1 XTS XT2OFF DIVA_0 DIVA_1 DIVA_2 DIVA_3 equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ 0x0056 0x0057 0x0058 0x0053 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x00 0x10 0x20 0x30 ; Definition to show that Module is avai ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; DCO Clock Frequency Control Basic Clock System Control 1 Basic Clock System Control 2 Basic Clock System Control 3 Modulation Modulation Modulation Modulation Modulation DCO Select DCO Select DCO Select Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 0 1 2

Range Select Bit 0 Range Select Bit 1 Range Select Bit 2 Range Select Bit 3 ACLK Divider 0 ACLK Divider 1 LFXTCLK 0:Low Freq. / 1: High Freq. Enable XT2CLK ACLK ACLK ACLK ACLK Divider Divider Divider Divider 0: 1: 2: 3: /1 /2 /4 /8

DIVS0 DIVS1 SELS K/LFXTCLK DIVM0 DIVM1 SELM0 SELM1 DIVS_0 DIVS_1 DIVS_2 DIVS_3 DIVM_0 DIVM_1 DIVM_2 DIVM_3 SELM_0 SELM_1 SELM_2 SELM_3 LFXT1OF ag XT2OF XCAP0 XCAP1 LFXT1S0 LFXT1S1 XT2S0 XT2S1 XCAP_0 XCAP_1 XCAP_2 XCAP_3 LFXT1S_0 LFXT1S_1 LFXT1S_2 LFXT1S_3 l XT2S_0 XT2S_1 XT2S_2 XT2S_3 ;;; ;;; Comparator A ;;;

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ

0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x00 0x02 0x04 0x06 0x00 0x10 0x20 0x30 0x00 0x40 0x80 0xC0 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x00 0x04 0x08 0x0C 0x00 0x10 0x20 0x30 0x00 0x40 0x80 0xC0

; SMCLK Divider 0 ; SMCLK Divider 1 ; SMCLK Source Select 0:DCOCLK / 1:XT2CL ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; MCLK MCLK MCLK MCLK SMCLK SMCLK SMCLK SMCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK Divider 0 Divider 1 Source Select 0 Source Select 1 Divider Divider Divider Divider Divider Divider Divider Divider Source Source Source Source 0: 1: 2: 3: 0: 1: 2: 3: /1 /2 /4 /8 /1 /2 /4 /8 0: 1: 2: 3: DCOCLK DCOCLK XT2CLK/LFXTCLK LFXTCLK

Select Select Select Select

; Low/high Frequency Oscillator Fault Fl ; High frequency oscillator 2 fault flag ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; XIN/XOUT Cap 0 XIN/XOUT Cap 1 Mode 0 for LFXT1 XTS = 0 Mode 1 for LFXT1 XTS = 0 Mode 0 for XT2 Mode 1 for XT2 XIN/XOUT XIN/XOUT XIN/XOUT XIN/XOUT Mode Mode Mode Mode Mode Mode Mode Mode 0 1 2 3 0 1 2 3 Cap Cap Cap Cap : : : : 0 pF 6 pF 10 pF 12.5 pF : : : : Normal operation Reserved VLO Digital input signa

for for for for for for for for

LFXT1 LFXT1 LFXT1 LFXT1 XT2 XT2 XT2 XT2 : : : :

0.4 - 1 MHz 1 - 4 MHz 2 - 16 MHz Digital input signal

#define __MSP430_HAS_CAPLUS__ lable CACTL1 equ 0x0059

; Definition to show that Module is avai ; Comparator A Control 1

CACTL2 CAPD CAIFG CAIE CAIES :falling CAON CAREF0 CAREF1 CARSEL CAEX CAREF_0 CAREF_1 CAREF_2 CAREF_3 CAOUT CAF P2CA0 P2CA1 P2CA2 P2CA3 P2CA4 CASHORT CAPD0 egister CAPD1 egister CAPD2 egister CAPD3 egister CAPD4 egister CAPD5 egister CAPD6 egister CAPD7 egister .0

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ .1 equ .2 equ .3 equ .4 equ .5 equ .6 equ .7

0x005A 0x005B 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x00 0x10 0x20 0x30 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80

; Comparator A Control 2 ; Comparator A Port Disable ; Comp. A Interrupt Flag ; Comp. A Interrupt Enable ; Comp. A Int. Edge Select: 0:rising / 1 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. Comp. A A A A A A A A A A A A A A A A A enable Internal Internal Internal Exchange Int. Int. Int. Int. Ref. Ref. Ref. Ref. Reference Select 0 Reference Select 1 Reference Enable Inputs Select Select Select Select 0 1 2 3 : : : : Off 0.25*Vcc 0.5*Vcc Vt

Output Enable Output Filter +Terminal Multiplexer -Terminal Multiplexer -Terminal Multiplexer -Terminal Multiplexer +Terminal Multiplexer Short + and - Terminals

; Comp. A Disable Input Buffer of Port R ; Comp. A Disable Input Buffer of Port R ; Comp. A Disable Input Buffer of Port R ; Comp. A Disable Input Buffer of Port R ; Comp. A Disable Input Buffer of Port R ; Comp. A Disable Input Buffer of Port R ; Comp. A Disable Input Buffer of Port R ; Comp. A Disable Input Buffer of Port R

;;; ;;; Flash Memory ;;; #define __MSP430_HAS_FLASH2__ lable FCTL1 FCTL2 FCTL3 FRKEY FWKEY FXKEY ERASE equ equ equ equ equ equ equ 0x0128 0x012A 0x012C 0x9600 0xA500 0x3300 0x0002 ; Definition to show that Module is avai ; FLASH Control 1 ; FLASH Control 2 ; FLASH Control 3 ; Flash key returned by read ; Flash key for write ; for use with XOR instruction ; Enable bit for Flash segment erase

MERAS WRT BLKWRT SEGWRT segment write

equ equ equ equ

0x0004 0x0040 0x0080 0x0080 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0000 0x0040 0x0080 0x00C0 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080

; ; ; ;

Enable bit for Enable bit for Enable bit for old definition

Flash mass erase Flash write Flash segment write -- Enable bit for Flash

FN0 equ 0 to FN5 according to: FN1 equ N1 + FN0 + 1 FN2 equ FN3 equ FN4 equ FN5 equ FSSEL0 equ from USART SSELx FSSEL1 equ FSSEL_0 FSSEL_1 FSSEL_2 FSSEL_3 equ equ equ equ

; Divide Flash clock by 1 to 64 using FN ; 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*F

; Flash clock select 0 -- to distinguish ; Flash clock select 1 ; ; ; ; ; ; ; ; ; Flash Flash Flash Flash clock clock clock clock select: select: select: select: 0 1 2 3 ACLK MCLK SMCLK SMCLK

BUSY equ KEYV equ ACCVIFG equ WAIT equ LOCK equ y EMEX equ LOCKA equ is locked read only FAIL equ

Flash busy: 1 Flash Key violation flag Flash Access violation flag Wait flag for segment write Lock bit: 1 - Flash is locked read onl

; Flash Emergency Exit ; Segment A Lock bit: read = 1 - Segment ; Last Program or Erase failed

;;; ;;; DIGITAL I/O Port1/2 Pull up / Pull down Resistors ;;; #define __MSP430_HAS_PORT1_R__ lable #define __MSP430_HAS_PORT2_R__ lable P1IN P1OUT P1DIR P1IFG P1IES P1IE P1SEL P1SEL2 P1REN P2IN P2OUT P2DIR P2IFG P2IES P2IE P2SEL equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0041 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E ; Definition to show that Module is avai ; Definition to show that Module is avai ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Selection Selection 2 Resistor Enable Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Selection

P2SEL2 P2REN

equ equ

0x0042 0x002F

; Port 2 Selection 2 ; Port 2 Resistor Enable

;;; ;;; DIGITAL I/O Port3 Pull up / Pull down Resistors ;;; #define __MSP430_HAS_PORT3_R__ lable P3IN P3OUT P3DIR P3SEL P3SEL2 P3REN ;;; ;;; Timer0_A3 ;;; #define __MSP430_HAS_TA3__ lable TA0IV TA0CTL TA0CCTL0 TA0CCTL1 TA0CCTL2 TA0R TA0CCR0 TA0CCR1 TA0CCR2 equ equ equ equ equ equ equ equ equ 0x012E 0x0160 0x0162 0x0164 0x0166 0x0170 0x0172 0x0174 0x0176 ; Definition to show that Module is avai ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Timer0_A3 Timer0_A3 Timer0_A3 Timer0_A3 Timer0_A3 Timer0_A3 Timer0_A3 Timer0_A3 Timer0_A3 Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer A A A A A A A A A A A A A A A A A A A A A A Interrupt Vector Word Control Capture/Compare Control 0 Capture/Compare Control 1 Capture/Compare Control 2 Capture/Compare 0 Capture/Compare 1 Capture/Compare 2 equ equ equ equ equ equ 0x0018 0x0019 0x001A 0x001B 0x0043 0x0010 ; Definition to show that Module is avai ; ; ; ; ; ; Port Port Port Port Port Port 3 3 3 3 3 3 Input Output Direction Selection Selection 2 Resistor Enable

; Alternate register names TAIV equ TA0IV TACTL equ TA0CTL TACCTL0 equ TA0CCTL0 TACCTL1 equ TA0CCTL1 TACCTL2 equ TA0CCTL2 TAR equ TA0R TACCR0 equ TA0CCR0 TACCR1 equ TA0CCR1 TACCR2 equ TA0CCR2 ; Alternate register names 2 CCTL0 equ TACCTL0 CCTL1 equ TACCTL1 CCTL2 equ TACCTL2 CCR0 equ TACCR0 CCR1 equ TACCR1 CCR2 equ TACCR2 TASSEL1 TASSEL0 ID1 ID0 MC1 MC0 TACLR equ equ equ equ equ equ equ 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0004

Interrupt Vector Word Control Capture/Compare Control 0 Capture/Compare Control 1 Capture/Compare Control 2 Capture/Compare 0 Capture/Compare 1 Capture/Compare 2 Capture/Compare Capture/Compare Capture/Compare Capture/Compare Capture/Compare Capture/Compare Control 0 Control 1 Control 2 0 1 2 0 1 1 0

clock source select clock source select clock input divider clock input divider mode control 1 mode control 0 counter clear

TAIE TAIFG MC_0 MC_1 MC_2 MC_3 ID_0 ID_1 ID_2 ID_3 TASSEL_0 TASSEL_1 TASSEL_2 TASSEL_3 CM1 CM0 CCIS1 CCIS0 SCS SCCI CAP OUTMOD2 OUTMOD1 OUTMOD0 CCIE CCI OUT COV CCIFG OUTMOD_0 OUTMOD_1 OUTMOD_2 OUTMOD_3 OUTMOD_4 OUTMOD_5 OUTMOD_6 OUTMOD_7 CCIS_0 CCIS_1 CCIS_2 CCIS_3 CM_0 CM_1 CM_2 CM_3

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ

0x0002 0x0001 0x0000 0x0010 0x0020 0x0030 0x0000 0x0040 0x0080 0x00C0 0x0000 0x0100 0x0200 0x0300 0x8000 0x4000 0x2000 0x1000 0x0800 0x0400 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 0x0000 0x0020 0x0040 0x0060 0x0080 0x00A0 0x00C0 0x00E0 0x0000 0x1000 0x2000 0x3000 0x0000 0x4000 0x8000 0xC000 0x0000 0x0002 0x0004 0x0006 0x0008

; Timer A counter interrupt enable ; Timer A counter interrupt flag ; Timer A mode control: 0 - Stop ; Timer A mode control: 1 - Up to CCR0 ; Timer A mode control: 2 - Continous up ; ; ; ; ; ; Timer Timer Timer Timer Timer Timer A A A A A A mode control: 3 - Up/Down input divider: 0 - /1 input divider: 1 - /2 input divider: 2 - /4 input divider: 3 - /8 clock source select: 0 - TACLK

; Timer A clock source select: 1 - ACLK ; Timer A clock source select: 2 - SMCLK ; Timer A clock source select: 3 - INCLK ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Capture mode 1 Capture mode 0 Capture input select 1 Capture input select 0 Capture sychronize Latched capture signal read Capture mode: 1 /Compare mode : 0 Output mode 2 Output mode 1 Output mode 0 Capture/compare interrupt enable Capture input signal read PWM Output signal if output mode 0 Capture/compare overflow flag Capture/compare interrupt flag PWM output mode: 0 - output only PWM output mode: 1 - set PWM output mode: 2 - PWM toggle/reset PWM output mode: 3 - PWM set/reset PWM output mode: 4 - toggle PWM output mode: 5 - Reset PWM output mode: 6 - PWM toggle/set PWM output mode: 7 - PWM reset/set Capture input select: 0 - CCIxA Capture input select: 1 - CCIxB Capture input select: 2 - GND Capture input select: 3 - Vcc Capture mode: 0 - disabled Capture mode: 1 - pos. edge Capture mode: 1 - neg. edge Capture mode: 1 - both edges No Interrupt pending TA0CCR1_CCIFG TA0CCR2_CCIFG Reserved Reserved

; T0_A3IV Definitions TA0IV_NONE equ TA0IV_TACCR1 equ TA0IV_TACCR2 equ TA0IV_6 equ TA0IV_8 equ

TA0IV_TAIFG ;;; ;;; Timer1_A3 ;;;

equ

0x000A

; TA0IFG

#define __MSP430_HAS_T1A3__ lable TA1IV TA1CTL TA1CCTL0 TA1CCTL1 TA1CCTL2 TA1R TA1CCR0 TA1CCR1 TA1CCR2 equ equ equ equ equ equ equ equ equ 0x011E 0x0180 0x0182 0x0184 0x0186 0x0190 0x0192 0x0194 0x0196

; Definition to show that Module is avai ; ; ; ; ; ; ; ; ; Timer1_A3 Timer1_A3 Timer1_A3 Timer1_A3 Timer1_A3 Timer1_A3 Timer1_A3 Timer1_A3 Timer1_A3 Interrupt Vector Word Control Capture/Compare Control 0 Capture/Compare Control 1 Capture/Compare Control 2 Capture/Compare 0 Capture/Compare 1 Capture/Compare 2

; Bits are already defined within the Timer0_Ax ; T1_A3IV Definitions TA1IV_NONE equ TA1IV_TACCR1 equ TA1IV_TACCR2 equ TA1IV_TAIFG equ ;;; ;;; USCI ;;; #define __MSP430_HAS_USCI__ lable UCA0CTL0 UCA0CTL1 UCA0BR0 UCA0BR1 UCA0MCTL UCA0STAT UCA0RXBUF UCA0TXBUF UCA0ABCTL UCA0IRTCTL UCA0IRRCTL UCB0CTL0 UCB0CTL1 UCB0BR0 UCB0BR1 UCB0I2CIE UCB0STAT UCB0RXBUF UCB0TXBUF UCB0I2COA UCB0I2CSA ; UART-Mode Bits equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x005D 0x005E 0x005F 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F 0x0118 0x011A ; Definition to show that Module is avai ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 Control Register 0 Control Register 1 Baud Rate 0 Baud Rate 1 Modulation Control Status Register Receive Buffer Transmit Buffer LIN Control IrDA Transmit Control IrDA Receive Control Control Register 0 Control Register 1 Baud Rate 0 Baud Rate 1 I2C Interrupt Enable Register Status Register Receive Buffer Transmit Buffer I2C Own Address I2C Slave Address 0x0000 0x0002 0x0004 0x000A ; ; ; ; No Interrupt pending TA1CCR1_CCIFG TA1CCR2_CCIFG TA1IFG

UCPEN UCPAR UCMSB UC7BIT -bits UCSPB UCMODE1 UCMODE0 UCSYNC

equ equ equ equ equ equ equ equ

0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x08 0x80 0x40 0x20 0x10 0x00 0x02 0x04 0x06 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x20 0x10 0x08 0x04 0x02 0x20 0x10 0x08 0x04 0x02 0x00 0x40 0x80 0xC0 0x80 0x40 0x20 0x10 0x08

; Async. Mode: Parity enable ; Async. Mode: Parity 0:odd / 1:even ; Async. Mode: MSB first 0:LSB / 1:MSB ; Async. Mode: Data Bits 0:8-bits / 1:7 ; Async. Mode: Stop Bits 0:one / 1: two ; Async. Mode: USCI Mode 1 ; Async. Mode: USCI Mode 0 ; Sync-Mode 0:UART-Mode / 1:SPI-Mode ; Sync. Mode: Clock Phase ; Sync. Mode: Clock Polarity ; Sync. Mode: Master Select ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 10-bit Address Mode 10-bit Slave Address Mode Multi-Master Environment reserved Sync. Mode: USCI Mode: 0 Sync. Mode: USCI Mode: 1 Sync. Mode: USCI Mode: 2 Sync. Mode: USCI Mode: 3 USCI 0 Clock Source Select 1 USCI 0 Clock Source Select 0 RX Error interrupt enable Break interrupt enable Dormant Sleep Mode Send next Data as Address Send next Data as Break USCI Software Reset reserved reserved reserved reserved reserved reserved Transmit/Receive Select/Flag Transmit NACK Transmit STOP Transmit START USCI 0 Clock Source: 0 USCI 0 Clock Source: 1 USCI 0 Clock Source: 2 USCI 0 Clock Source: 3 USCI USCI USCI USCI USCI First Stage Modulation Select 3 First Stage Modulation Select 2 First Stage Modulation Select 1 First Stage Modulation Select 0 Second Stage Modulation Select 2

; SPI-Mode Bits UCCKPH equ UCCKPL equ UCMST equ ; I2C-Mode Bits UCA10 equ UCSLA10 equ UCMM equ ; UCMODE_0 equ UCMODE_1 equ UCMODE_2 equ UCMODE_3 equ ; UART-Mode Bits UCSSEL1 equ UCSSEL0 equ UCRXEIE equ UCBRKIE equ UCDORM equ UCTXADDR equ UCTXBRK equ UCSWRST equ ; SPI-Mode Bits ; ; ; ; ; ; I2C-Mode Bits ; UCTR equ UCTXNACK equ UCTXSTP equ UCTXSTT equ UCSSEL_0 equ UCSSEL_1 equ UCSSEL_2 equ UCSSEL_3 equ UCBRF3 UCBRF2 UCBRF1 UCBRF0 UCBRS2 equ equ equ equ equ

UCBRS1 UCBRS0 UCOS16 UCBRF_0 UCBRF_1 UCBRF_2 UCBRF_3 UCBRF_4 UCBRF_5 UCBRF_6 UCBRF_7 UCBRF_8 UCBRF_9 UCBRF_10 UCBRF_11 UCBRF_12 UCBRF_13 UCBRF_14 UCBRF_15 UCBRS_0 UCBRS_1 UCBRS_2 UCBRS_3 UCBRS_4 UCBRS_5 UCBRS_6 UCBRS_7 UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR UCBUSY UCIDLE ; ; ; ; UCNACKIE UCSTPIE UCSTTIE UCALIE UCSCLLOW UCGC UCBBUSY UCNACKIFG UCSTPIFG UCSTTIFG UCALIFG UCIRTXPL5 UCIRTXPL4 UCIRTXPL3

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ

0x04 0x02 0x01 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x02 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20

; USCI Second Stage Modulation Select 1 ; USCI Second Stage Modulation Select 0 ; USCI 16-times Oversampling enable ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI USCI First First First First First First First First First First First First First First First First Second Second Second Second Second Second Second Second Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Stage Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: Modulation: 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7

Listen mode Frame Error Flag Overrun Error Flag Parity Error Flag Break received RX Error Flag Address received Flag Busy Flag Idle line detected Flag

equ equ equ equ equ equ equ equ equ equ equ equ equ equ

reserved reserved reserved reserved NACK Condition interrupt enable STOP Condition interrupt enable START Condition interrupt enable Arbitration Lost interrupt enable SCL low General Call address received Flag Bus Busy Flag NAK Condition interrupt Flag STOP Condition interrupt Flag START Condition interrupt Flag Arbitration Lost interrupt Flag

; IRDA Transmit Pulse Length 5 ; IRDA Transmit Pulse Length 4 ; IRDA Transmit Pulse Length 3

UCIRTXPL2 UCIRTXPL1 UCIRTXPL0 UCIRTXCLK UCIREN UCIRRXFL5 UCIRRXFL4 UCIRRXFL3 UCIRRXFL2 UCIRRXFL1 UCIRRXFL0 UCIRRXPL UCIRRXFE ; ; UCDELIM1 UCDELIM0 UCSTOE UCBTOE ; UCABDEN UCGCEN UCOA9 UCOA8 UCOA7 UCOA6 UCOA5 UCOA4 UCOA3 UCOA2 UCOA1 UCOA0 UCSA9 UCSA8 UCSA7 UCSA6 UCSA5 UCSA4 UCSA3 UCSA2 UCSA1 UCSA0

equ equ equ equ equ equ equ equ equ equ equ equ equ

0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x8000 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001

; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;

IRDA IRDA IRDA IRDA IRDA IRDA IRDA IRDA IRDA IRDA IRDA IRDA IRDA

Transmit Pulse Length 2 Transmit Pulse Length 1 Transmit Pulse Length 0 Transmit Pulse Clock Select Encoder/Decoder enable Receive Receive Receive Receive Receive Receive Receive Receive Filter Length 5 Filter Length 4 Filter Length 3 Filter Length 2 Filter Length 1 Filter Length 0 Input Polarity Filter enable

equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ

reserved reserved Break Sync Delimiter 1 Break Sync Delimiter 0 Sync-Field Timeout error Break Timeout error reserved Auto Baud Rate detect enable I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C I2C General Call enable Own Address 9 Own Address 8 Own Address 7 Own Address 6 Own Address 5 Own Address 4 Own Address 3 Own Address 2 Own Address 1 Own Address 0 Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Address Address Address Address Address Address Address Address Address Address 9 8 7 6 5 4 3 2 1 0

;;; ;;; WATCHDOG TIMER ;;; #define __MSP430_HAS_WDT__ lable WDTCTL equ 0x0120 ; Definition to show that Module is avai ; Watchdog Timer Control

; The bit names have been prefixed with "WDT" WDTIS0 equ 0x0001 WDTIS1 equ 0x0002 WDTSSEL equ 0x0004

WDTCNTCL WDTTMSEL WDTNMI WDTNMIES WDTHOLD WDTPW

equ equ equ equ equ equ

0x0008 0x0010 0x0020 0x0040 0x0080 0x5A00

; WDT-interval times [1ms] coded with Bits 0-2 ; WDT is clocked by fSMCLK assumed 1MHz WDT_MDLY_32 equ WDTPW+WDTTMSEL+WDTCNTCL nterval default WDT_MDLY_8 equ WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0 " WDT_MDLY_0_5 equ WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 " WDT_MDLY_0_064 equ WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0 s " ; WDT is clocked by fACLK assumed 32KHz WDT_ADLY_1000 equ WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL " WDT_ADLY_250 equ WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0 " WDT_ADLY_16 equ WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1 " WDT_ADLY_1_9 equ WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 " ; Watchdog mode -> reset after expired time ; WDT is clocked by fSMCLK assumed 1MHz WDT_MRST_32 equ WDTPW+WDTCNTCL nterval default WDT_MRST_8 equ WDTPW+WDTCNTCL+WDTIS0 " WDT_MRST_0_5 equ WDTPW+WDTCNTCL+WDTIS1 " WDT_MRST_0_064 equ WDTPW+WDTCNTCL+WDTIS1+WDTIS0 s " ; WDT is clocked by fACLK assumed 32KHz WDT_ARST_1000 equ WDTPW+WDTCNTCL+WDTSSEL " WDT_ARST_250 equ WDTPW+WDTCNTCL+WDTSSEL+WDTIS0 " WDT_ARST_16 equ WDTPW+WDTCNTCL+WDTSSEL+WDTIS1 " WDT_ARST_1_9 equ WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 " ; ; ; ; INTERRUPT CONTROL These two bits are defined in the Special Function Registers WDTIE 0x01 WDTIFG 0x01

; 32ms i ; 8ms ; 0.5ms ; 0.064m

; 1000ms ; 250ms ; 16ms ; 1.9ms

; 32ms i ; 8ms ; 0.5ms ; 0.064m

; 1000ms ; 250ms ; 16ms ; 1.9ms

;;; ;;; Calibration Data in Info Mem ;;; CALDCO_16MHZ equ 0x10F8 ; DCOCTL Calibration Data for 16MHz

CALBC1_16MHZ CALDCO_12MHZ CALBC1_12MHZ CALDCO_8MHZ CALBC1_8MHZ CALDCO_1MHZ CALBC1_1MHZ

equ equ equ equ equ equ equ

0x10F9 0x10FA 0x10FB 0x10FC 0x10FD 0x10FE 0x10FF

; ; ; ; ; ; ;

BCSCTL1 DCOCTL BCSCTL1 DCOCTL BCSCTL1 DCOCTL BCSCTL1

Calibration Calibration Calibration Calibration Calibration Calibration Calibration

Data Data Data Data Data Data Data

for for for for for for for

16MHz 12MHz 12MHz 8MHz 8MHz 1MHz 1MHz

;;; ;;; Interrupt Vectors offset from 0xFFE0 ;;; PORT1_VECTOR PORT2_VECTOR ADC10_VECTOR USCIAB0TX_VECTOR USCIAB0RX_VECTOR TIMER0_A1_VECTOR TIMER0_A0_VECTOR WDT_VECTOR COMPARATORA_VECTOR TIMER1_A1_VECTOR TIMER1_A0_VECTOR NMI_VECTOR RESET_VECTOR ] ;;; ;;; End of Modules ;;; equ equ equ equ equ equ equ equ equ equ equ equ equ 0x0004 0x0006 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E ; ; ; ; ; ; ; ; ; ; ; ; ; 0xFFE4 0xFFE6 0xFFEA 0xFFEC 0xFFEE 0xFFF0 0xFFF2 0xFFF4 0xFFF6 0xFFF8 0xFFFA 0xFFFC 0xFFFE Port 1 Port 2 ADC10 USCI A0/B0 Transmit USCI A0/B0 Receive Timer0A CC1, TA0 Timer0_A CC0 Watchdog Timer Comparator A Timer1_A CC1-4, TA1 Timer1_A CC0 Non-maskable Reset [Highest Priority