The model consists of a main code .Please note the processes are described in or der .

Interfaces:Inputs:clk (Clock ) 4 device requests( req_a , req_b , req_c ,req_d ) Outputs :4 set of 3 led signals ( red , yellow , green )

Architecture :-

System clock generator The module generates the system clock . At present kept to be board clock / 3 . The system runs on system clock . Request capture :4 request counter which develop a count for request for each disk . Counter update process:At every posedge of sys_clk , update the counter values . COunter increments a s the request comes in and decrements if a particular request was processed . Counter compare and enable generation :This is enabled using a state machine . IN_PROCESS state :- Compare the counter values and generate the enable . DElay :- Logic leds are lit up depending on the counter buffer state .

Output values are assigned off from the variable registers to the outputs.