library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.

all; entity block_1 port ( CLK : WE : A : DATA_IN : DATA_OUT : ); end block_1 is in in in in out std_logic; std_logic; std_logic_vector; std_logic_vector; std_logic_vector

architecture Behavioral of block_1 is type RAM is array (511 to 0) of std_logic_vector (7 downto 0); signal blockram : RAM; begin process(CLK) begin id rising_edge(CLK) then if WE='1' then blockram (WA)<=DATA_IN; end if; end if; process (CLK) begin if rising_edge (CLK) then DATA_OUT<=blockram (RA); end if: end process; end behivoral;