for(i = 0 ; i < `C_NUM_OF_DEC ; i = i + 1) begin if(i == (`C_NUM_OF_DEC-1)) begin // Last decoder always @(*)//`C_RST_MODE) if (rst_n == `C_LOW) begin bet_init_0_r[i]

<= `C_LAST_DEC_BET_INIT_LOG_ONE ; end else begin if(dcl_dp_r2_en[i]) begin //if(last_sw_r & eob_bet_p_c) begin if(last_sw_p_c & eob_bet_p_c) begin if(~dcl_intlv) begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ONE ; end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_SAME_STATE;//`C_LAST _DEC_BET_INIT_LOG_ZERO; end end else if (bet_guard_vld[i]) begin bet_init_0_r[i] <= grd_bet_st_0_c[i]; end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ONE ; end end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ONE ; end end end else begin // Other than Last decoder // Register bet and its qualifier always @(*)//`C_RST_MODE) if (rst_n == `C_LOW) begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ZERO;//`C_LAST_DEC_BET_I NIT_SAME_STATE; end else if(i_cl _en) if(dcl_dp_r2_en[i]) begin if(bet_guard_vld[i] ) begin bet_init_0_r[i] <= grd_bet_st_0_c[i]; end //else if (last_sw_r & eob_bet_p_c) begin else if (last_sw_p_c & eob_bet_p_c) begin `ifdef C_NUM_OF_DEC_8 case(dcl_nod[1:0]) 2'h3 : begin if(i == 7) begin // 8 decoders in compile time and 8th d ecoder bet_init_0_r[i] <= (dcl_intlv) ? `C_LAST_DEC_BET_INIT_ SAME_STATE : `C_LAST_DEC_BET_INIT_LOG_ONE; end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ZERO; end

end

2'h2 : begin if(i == 3) begin // 4 decoders in compile time and 4th d ecoder bet_init_0_r[i] <= (dcl_intlv) ? `C_LAST_DEC_BET_INIT_ SAME_STATE : `C_LAST_DEC_BET_INIT_LOG_ONE; end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ZERO; end end 2'h1 : begin if(i == 1) begin // 2 decoders in compile time and 2nd decoder bet_init_0_r[i] <= (dcl_intlv) ? `C_LAST_DEC_BET_INIT_ SAME_STATE : `C_LAST_DEC_BET_INIT_LOG_ONE; end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ZERO; end end 2'h0 : begin bet_init_0_r[i] <= (dcl_intlv) ? `C_LAST_DEC_BET_INIT_SA ME_STATE : `C_LAST_DEC_BET_INIT_LOG_ONE; end endcase `endif `ifdef C_NUM_OF_DEC_4 case(dcl_nod[1:0]) 2'h2 : begin if(i == 3) begin // 4 decoders in compile time and 4th d ecoder bet_init_0_r[i] <= (dcl_intlv) ? `C_LAST_DEC_BET_INIT_ SAME_STATE : `C_LAST_DEC_BET_INIT_LOG_ONE; end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ZERO; end end 2'h1 : begin if(i == 1) begin // 4 decoders in compile time and 2nd d ecoder bet_init_0_r[i] <= (dcl_intlv) ? `C_LAST_DEC_BET_INIT_ SAME_STATE : `C_LAST_DEC_BET_INIT_LOG_ONE; end else begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_LOG_ZERO; end end 2'h0 : begin bet_init_0_r[i] <= (dcl_intlv) ? `C_LAST_DEC_BET_INIT_SA ME_STATE : `C_LAST_DEC_BET_INIT_LOG_ONE; end default : begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_SAME_STATE; end

endcase `endif end end else begin if(dcl_iter_over) begin bet_init_0_r[i] <= `C_LAST_DEC_BET_INIT_SAME_STATE; end else end end assign muxed_bet_st_0_c[i] LAST_DEC_BET_INIT_SAME_STATE; assign muxed_bet_st_1_c[i] AST_DEC_BET_INIT_SAME_STATE; assign muxed_bet_st_2_c[i] AST_DEC_BET_INIT_SAME_STATE; assign muxed_bet_st_3_c[i] AST_DEC_BET_INIT_SAME_STATE; assign muxed_bet_st_4_c[i] AST_DEC_BET_INIT_SAME_STATE; assign muxed_bet_st_5_c[i] AST_DEC_BET_INIT_SAME_STATE; assign muxed_bet_st_6_c[i] AST_DEC_BET_INIT_SAME_STATE; assign muxed_bet_st_7_c[i] AST_DEC_BET_INIT_SAME_STATE; end endgenerate =(bet_guard_vld[i]) ? grd_bet_st_0_c[i] : `C_

=(bet_guard_vld[i]) ? grd_bet_st_1_c[i] : `C_L =(bet_guard_vld[i]) ? grd_bet_st_2_c[i] : `C_L =(bet_guard_vld[i]) ? grd_bet_st_3_c[i] : `C_L =(bet_guard_vld[i]) ? grd_bet_st_4_c[i] : `C_L =(bet_guard_vld[i]) ? grd_bet_st_5_c[i] : `C_L =(bet_guard_vld[i]) ? grd_bet_st_6_c[i] : `C_L =(bet_guard_vld[i]) ? grd_bet_st_7_c[i] : `C_L