`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
// Company:
// Engineer:
//
// Create Date:
10:14:31 09/04/2012
// Design Name:
// Module Name:
apb_timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
module apb_timer(bclk,rst,psel,pwrite,tc, addr, wdata, Int,clk,mode,en, rdata,lo
ad_data, value);
input bclk,rst,psel,pwrite,tc;
input [15:0] addr;
input [31:0] wdata;
output Int,clk,mode,en;
output [31:0] rdata,load_data;
input [4:0] value;
reg Int,clk;
reg [7:0] control;
reg [31:0] rdata;
reg [4:0] count;
wire en =control[7];
wire mode = control[6];
wire[1:0] prescale = control[3:2];

always@(pwrite or psel or addr or control or value)

begin
if(psel && (!pwrite))
case(addr)
4 : rdata = {28'h0000000,value};
8 : rdata = {24'h00000,control};
default : rdata = 32'h0;
endcase
else
rdata = 32'd0;
end
always@(posedge clk or posedge rst)
begin
if(rst)
control <= 8'h00;
else if (psel && pwrite && addr == 16'h0008)
control <= wdata[7:0];
end

wire load = (psel && pwrite && addr == 16'h0000);

always@(posedge clk or posedge rst)
begin
if(rst)
count <= 2'h0;
else
begin
count <= count + 1;
end
end
always@(count or prescale or bclk)
begin
case(prescale)
2'b00 : clk = bclk;
2'b01 : clk = count[0];
2'b10 : clk = count[1];
default : clk = bclk;
endcase
end
always@(posedge clk or posedge rst)
begin
if(rst)
Int <=0;
else if(tc == 1)
Int <= 1;
else if (pwrite && psel && addr == 16'h000c)
Int <= 0;
end
endmodule