Chapter 6: Built-In Self-Test

Cheng-Wen Wu
Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University

Outline
Introduction Off-line BIST Test generation and response analysis for BIST Pseudo random pattern generation Signature analysis Multiple-input signature register (MISR) Examples
STUMPS PS-BIST

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Critical Issues in Testing

How are test patterns generated?
Exhaustive/pseudoexhaustive Random/pseudorandom Functional Algorithmic

How are test patterns applied?

ATE BIST

How are outputs handled?

Comparison (stored in tester or gold unit) Referenceless (compaction, code verification)
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Built-In Self-Test (BIST)

Test patterns generated on-chip higher controllability (more control points) Response evaluated on-chip higher observability (more observation points) Test can be on-line (concurrent) or off-line Test can run at circuit speed more realistic; shorter test time; easier delay testing External test equipment greatly simplified, or even totally eliminated Easily adopting to engineering changes Easier burn-in support Reduced development and diagnosis effort at IC, board, and system levels
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On-Line BIST
Concurrent (EDAC, NMR, totally selfchecking checker, etc.)
Coding or modular redundancy techniques

(fault tolerance)
Instantaneous correction of errors caused

by temporary or permanent faults

Nonconcurrent (diagnostic routines)

Carried out while a system is in an idle

state
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Off-Line BIST

TPG

Functional Circuit (CUT)

RA

Controller BIST Mode

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Go/No-go
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Test Pattern Generation for BIST

Pre-stored TPG, e.g., ROM or shift register Exhaustive TPG, e.g., binary counter Pseudo-exhaustive TPG, e.g., syndrome driver counter, constant-weight counter, combined LFSR and SR, combined LFSR and XOR gates, condensed LFSR, and cyclic LFSR Pseudo-random pattern generator (PRPG), e.g., weighted PG and adaptive PG Functional TPG
Embedded deterministic TPG
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Response Analysis for BIST

Check-sum Ones counting Syndrome analysis Transition counting Parity checking Signature analysis Walsh-Hadamard spectra

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Linear Feedback Shift Register (LFSR)

Linear circuit: one that contains only XOR gates and delay elements; no AND/OR gates
Linear operations: modulo addition, modulo scalar

multiplication, & delay Nonlinear operations: AND, OR, NAND, NOR, etc.

LFSR can be both the test generator (pseudorandom pattern generator) and response analyzer (signature analyzer) Registers often occur naturally in the design
Reconfigured into LFSRs during test mode
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LFSR Pseudo Random Pattern Generator

D1

D2

D3

D4

D5

an=an-3+an-5
n

c(x)=x5+x3+1

M-sequence: maximum-length sequence

Length is 2 -1, excluding the all-0 pattern

Better than counter

More random, even for any small window of the m-

sequence
110 011 111 101 100 010 001

Eg., n=3, c(x)=x3+x+1:

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Characteristics of the M-Sequence

Period is 2n-1 for an n-stage LFSR
n In any window of width n, each of the 2 -1 nonzero binary n-tuples is seen exactly once in a period [Window Property]

In each bit position in a period:

There are 2 1s and 2 -1 0s Half of the runs have length 1, 1/4 have length 2, 1/8 have
n-1 n-1

length 3, etc. Runs of 1s and 0s terminate with runs of length n and n-1, respectively. Except for these terminating lengths, there are equally many runs of 1s and 0s. The total number of n-1 1-runs equals that of 0-runs. Number of runs in a period is 2 [Run Property] n-1 The number of transitions is 2 -1 [Transition Property]

The sum of any bit sequences and a cyclic shift of itself is another cyclic shift of itself [Shift-and-Add Property]
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LFSR Signature Register

c(x)=x5+x3+1 m(x)

D1

D2

D3

D4

D5

q(x)

Type 1

m(x)

D1

D2

D3

D4

D5

q(x)

Type 2 Type 2: m(x)=q(x)c(x)+s(x)

c(x)=x5 +x4 +x2+1

Signature (s(x)) is the final state of the LFSR Aliasing probability is close to 1/2n
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Type-2 LFSR
m(x)

D1

D2

D3

D4

D5

q(x)

c(x)=x5 +x4 +x2+1

m(x) =q(x)c(x) +s(x) Error syndrome: e(X)

Let m(x) = x4+x3+1(11001), and an erroneous input b(x) = x3+X+1(01011), then the error

syndrome is 1100101011 = 10010, and is represented by e(x) = x4+X

Erroneous input polynomial: b(x)=m(x)+e(x)

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LFSR Signature Analysis

Theorem: Input streams m(x) and b(x) have the same signature iff e(x) is a multiple of c(x). Theorem: If c(X) has 2 or more nonzero coefficients (i.e., at least 1 feedback term) then it can detect all single-bit errors. Theorem: For a k-bit response sequence, if all possible error patterns are equally likely, then the probability of failing to detect an error (i.e., the aliasing probability) by the LFSR of length n is
P = ( 2 k n 1) /( 2 k 1) 1 / 2 n.

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Multiple Input Signature Register (MISR)

CUT
I1 I2
D1

I3
D2

I4
D3

D4

The mathematical theory is a direct extension of the results of LFSR Aliasing probability is also close to 1/2n
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Primitive Polynomials
10 940 17 3 0 25 3 0 33 13 0 41 3 0 49 9 0 57 7 0 210 10 3 0 18 7 0 26 8 7 1 0 310 11 2 0 19 6 5 1 0 27 8 7 1 0 410 12 7 4 3 0 20 3 0 28 3 0 36 11 0 520 13 4 3 1 0 21 2 0 29 2 0 610 710 86510 16 5 3 2 0 24 4 3 1 0 32 28 27 10 40 21 19 20 48 28 27 10 56 22 21 10 64 4 3 1 0 14 12 11 15 1 0 10 22 1 0 23 5 0

30 16 15 31 3 0 10 39 4 0

34 15 14 35 2 0 10 42 23 22 43 6 5 1 10 0

37 12 10 38 6 5 1 20 0

44 27 26 45 4 3 1 10 0

46 21 20 47 5 0 10

50 27 26 51 16 15 52 3 0 10 10 58 19 0 59 22 21 60 1 0 10

53 16 15 54 37 36 55 24 0 10 10 61 16 15 62 57 56 63 1 0 10 10

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Linear Cellular Automata (CA)

0 0

CA rules:
111 110 101 100 011 010 001 000 Rule 90 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 Rule 150 1

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LHCA-Based PRPG
0

150

90

150

90

150

90

Most popular CA PRPG: interleaved cells with rules 150 and 90, respectively
Called linear hybrid CA (LHCA) As LFSR, aliasing probability = 1/2 No global feedback lines
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Higher hardware overhead than LFSR

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Logic BIST Approaches

Test-Per-Scan
Test applied after scan chains are filled, e.g., STUMPS [Bardell et al. 1982] Low area and performance overhead, but slow

Test-Per-Clock
Test applied and response compressed in every clock cycle, e.g., BILBO [Konemann et al., 1979] and circular BIST [Krasniewski et al., 1989]

Hybrid
PSBIST [Lin et al. 1993]

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STUMPS: Test-Per-Scan LBIST

P R P G
Scan Chain 1 Scan Chain 2

M I S R

CUT
Scan Chain n-1 Scan Chain n

Self-Test Using MISR and Parallel SRSG Full scan with multiple scan chains
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Test-Per-Clock LBIST
x Combinational Logic z Also based on scan design
Short test time At-speed testing
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y PRPG MISR Y
SI SO

Circular BIST
x LFSR
Mux
SI SO

Combinational Logic z MISR MISR

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Random-Pattern Resistant Faults

Problem with PRPG-based LBIST: random-pattern resistant faults
Long test sequence; low fault coverage

Solutions:
Weighted random pattern generator Test-point insertion Embedded patterns

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Weighted PRPG

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STUMPS with Phase Shifter

P R P G ...
Phase Shifter

Scan Chain 1 Scan Chain 2

M I S R

CUT
Scan Chain n-1 Scan Chain n

Phase shifter (PS) reduces the impact of structural dependencies Can support more scan chains than #FFs in PRPG
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Test Point Insertion

0 CP 0 OP 0 1 CP OP 1
V

CP S OP

Observation point: fanout Control point

Controlling value: fanin 0 for AND/NAND gate; 1 for OR/NOR gate Non-controlling value: gate Universal MUX
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Scan-Based PS-BIST with Test Points

PI
M U X
to cps

Combinational Logic
S C
from ops

PO
M I

L F S R P S

S R

Source: K.-T. Tim Cheng, UCSB

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BIST Design Rules

No unknown (X) values can be tolerated
Any unknown (X) value that propagates directly or indirectly

to the RA will corrupt the signature

X-bounding or X-blocking:
Any unknown (X) source in the BIST-ready core that can

propagate its unknown (X) value to the RA directly or indirectly must be blocked and fixed using a DFT repair approach

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At-Speed BIST: Skewed-Load

Capture aligned Skewed-load

Launch aligned Skewed-load

Staggered Skewed-load

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At-Speed BIST: Double-Capture

Aka: broad-side or launch-on-capture

Capture aligned Double-capture

Launch aligned Double-capture

Staggered Double-capture

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Typical Logic BIST Flow

Source: Mentor Graphics

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