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  • 12 Sram Overview

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    Madhu Yalaka
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    SRAM Design Increase Read Noise Margin Vi Vo b d >> b a Increase cell Vdd Increase Vth Vdd Vo Reduce wordline Vdd Don't allow readcurrent through cell SRAM Cell Design: Write Margin Vi Vi Vo Vdd Write Noise Margin Vo Vi SRAM Cell Sizing Min Size Tradeoffs 7-T cell Read / Write Circuitry Read Waveforms Write Waveforms 7-t Cell Layout Hiding gaps Area overheads Same configuration 8-T cell Lay

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    SRAM Design Increase Read Noise Margin Vi Vo b d >> b a Increase cell Vdd Increase Vth Vdd Vo Reduce wordline Vdd Don't allow readcurrent through cell SRAM Cell Design: Write Margin Vi Vi Vo Vdd Write Noise Margin Vo Vi SRAM Cell Sizing Min Size Tradeoffs 7-T cell Read / Write Circuitry Read Waveforms Write Waveforms 7-t Cell Layout Hiding gaps Area overheads Same configuration 8-T cell Lay

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    10 views14 pages

    12 Sram Overview

    Uploaded by

    Madhu Yalaka
    SRAM Design Increase Read Noise Margin Vi Vo b d >> b a Increase cell Vdd Increase Vth Vdd Vo Reduce wordline Vdd Don't allow readcurrent through cell SRAM Cell Design: Write Margin Vi Vi Vo Vdd Write Noise Margin Vo Vi SRAM Cell Sizing Min Size Tradeoffs 7-T cell Read / Write Circuitry Read Waveforms Write Waveforms 7-t Cell Layout Hiding gaps Area overheads Same configuration 8-T cell Lay

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    of 14

    SRAM Design

    Increase Read Noise Margin

    Vi Vo

    d >> a Increase cell Vdd Increase Vth

    Vdd Vo

    SNMHigh SNMLow Vi

    Reduce wordline Vdd Dont allow readcurrent through cell

    SRAM Cell Design: Write Margin

    Vi Vo

    Vdd Write Noise Margin Vo

    Vi

    How to Improve Write Margin

    Vi Vo

    a >> p Decrease Cell Vdd Increase WL Vdd

    Vdd Write Noise Margin Vo

    Vi

    SRAM Cell Sizing

    Min Size

    Tradeoffs Read Noise Margin Cell Read Current Write Noise Margin Cell Size

    d >> a d ~ 3 x a a >> p

    Layout of SRAM Cell

    [Takeda, et. al., JSSC, Jan 2006]

    7-T Cell

    [Takeda, et. al., JSSC, Jan 2006]

    Read/Write Circuitry

    [Takeda, et. al., JSSC, Jan 2006]

    Read Waveforms

    [Takeda, et. al., JSSC, Jan 2006]

    Write Waveforms

    [Takeda, et. al., JSSC, Jan 2006]

    7-T Cell Layout

    [Takeda, et. al., JSSC, Jan 2006]

    Hiding gaps

    [Takeda, et. al., JSSC, Jan 2006]

    Area overheads

    Same configuration
    [Takeda, et. al., JSSC, Jan 2006]

    Same Speed

    8-T Cell

    [Takeda, et. al., JSSC, Jan 2006]

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