Sir Syed University of Engineering and Technology Department of Electronics Engineering Mid Term Examination (Fall Semester 2009)

Instructions: 1. Attempt all questions, 2. All questions carry equal marks. Q Question 1: (a) Define i) MOSFET, ii) Integrated circuit, iii) Test cell, iv) Hardware description language. (b) Assume a microprocessor requires an area of 1cm2 a. How many ICs can be fabricated on an 8 in wafer b. If the yield for the microprocessor is 85%, calculate the average number of good chips. Conversions 1 cm = 10-2 m 1 in = 2.54 x 10 -2 m
Symbols m = meter in = inch cm = centi-meter Question 3: (a) Define MOSFET Transconductance. How can we increase it in a device? (Explain using its equation) (b) Current sources are an important component in circuit design whose simplistic figure is given below. Calculate the bias current ID of transistor. Assume n COX = 100 A / V2 and VTH = 0.6 V Let drain terminal be at 1.6 V

EE306 - VLSI Principles and Applications

09/11/2009 Friday

6th Semester

Time: 1 Hour Marks: 10

Question 2: (a) Explain any four major process steps in the integrated circuit fabrication. (b) If a positive photo-resist is used, then what will happen to the figure below after photolithography. What should we do further to grow an n-type region. (Note: Side view of Mask is shown)

Question 4: (a) Define MOSFET Depletion layer & Pinch Off (b) Draw the diagram for an NMOS at both points of operation A and B. ( Diagrams should show the respective shape of electron channel under the gate). Also name the respective region of operation.

Question 5: (a) Explain the significance of Mask in IC fabrication. Is IC layout important for making a Mask? (b) The detailed diagram of an NMOS is given in figure (b). If for this NMOS, the Mask for drain, gate and source contacts is drawn as in figure (c) then draw one Mask for n+ regions and one for gate.(Two separate Masks!)

(a) NMOS Circuit Symbol

(b) NMOS structural diagram (3D)

(c) Top view of Mask for Drain / Gate / Source contact points