module testgate;

reg a,b;
wire ot;
gate z(ot,a,b);
initial
begin
a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
end
endmodule
module gate(ot,a,b);
input a,b;
output ot;
wire w1,w2,w3,w4,w5,w6,w7;
inverter n1(w1,a);
nand2 nn1(w2,w1,b);
inverter n2(w3,w2);
inverter n3(w4,b);
nand2 na2(w5,w4,a);
inverter n4(w6,w5);
nor2 nr1(w7,w3,w6);
inverter n5(ot,w7);
endmodule
module nand2(ot,a,b);
input a,b;
output ot;
wire w;
supply1 vdd;
supply0 gnd;
pmos p1(ot,vdd,a);
pmos p2(ot,vdd,b);
nmos n1(ot,w,a);
nmos n2(w,gnd,b);
endmodule
module nor2(ot,a,b);
input a,b;
output ot;
wire w;
supply1 vdd;
supply0 gnd;
pmos p1(w,vdd,a);
pmos p2(ot,w,b);
nmos n1(ot,gnd,a);
nmos n2(ot,gnd,b);
endmodule
module inverter(ot,a);
input a;
output ot;
supply1 vdd;
supply0 gnd;
pmos p1(ot,vdd,a);

nmos n1(ot,gnd,a);
endmodule
module testgate;
reg a,b;
wire ot;
gate z(ot,a,b);
initial
begin
a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
end
endmodule