Dynalith Systems Application Note DS-AN-2007-10-002

A Simple DMA Controller Example

Version 1 Revision 0 Oct. 31, 2007 (Oct. 31, 2007) Dynalith Systems (http://www.dynalith.com) 335 Gwahang-No (373-1 Kusong-Dong), 3rd Fl. CHiPS B/D, KAIST, Yusong-Gu, Daejeon 305-701, Korea

Copyright notice
The contents in this document and codes along with it are prepared in the hope that it will be useful to understand iNCITE related products, but WITHOUT ANY WARRANTY.

1 Introduction
This example addresses a simple DMA (Direct Memory Access) controller using iNCITE[1]. As shown in Figure 1, the DMA moves data under the control of C program running in the host computer.

AHB Transactor

AMBA bus

SSRAM IF (dual port)

Figure 1 : Overall environment Figure 1 shows overall setup in order to test DMA along with FPGA. DMA testing program: C program tests the DMA. AHB transactor: A design block in the FPGA of the iNCITE takes AHB transaction requests from the Flash testing program and generates AHB transactions on the AHB bus.

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SSRAM

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DMA controller: A design block moves data without the intervention of processing core. AMBA bus SSRAM interface: A design block interfaces SSRAM. SSRAM: A SSRAM on the iNCITE board

2 DMA controller block

The DMA controller used in this example provides three AHB bus ports as shown in Figure 2; one is AHB slave and the other two are AHB master ports. DMA internal resources, i.e., CSR (Control and Status Register) are accessed through the AHB slave port and data movement is carried out between two AHB master ports. For more details will be found from [5].

AHB slave port Active-high interrupt

AHB master port

IRQ B AHB master port

ahb_dma

Figure 2: DMA block DMA has the following CSR. When GO bit of the Control register is set to 1, the DMA starts data movement according to other register value. On completion of data movement, IRQ bit of Status register is set to 1 if IE bit of Control register is 1. Table 1: DMA CSR
Name Control Address offset +0h width Bit# 32 31~3 2 DMA control register (default: 0x00) Dont care GO, DMA enable bit When set to 1, the DMA is enabled Otherwise, the DMA is disabled. This bit automatically clears itself when a whole data movement completes. DIR, data movement direction bit When set to 0, data moves from A to B Otherwise, B to A IE, interrupt enable bit When set to 1, interrupt is enabled Otherwise, interrupt is disabled DMA status register (default: 0x00) Dont care BUSY, busy flag This bit is set while DMA operation. Dont care description

Status

+4h

32 31~3 2 1

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A_start A_size A_stride A_leng B_start B_size B_stride B_leng

+8h +Ch +10h +14h +18h +1Ch +20h +24h

32 32 32 32 32 32 32 32

IRQ, interrupt flag This bit is set when an interrupt is pending. Writing to 1 to this bit clears interrupt. The interrupt flag is set when a whole data movement completes. Starting address Size of each transfer; 1, 2, 4 are possible. Skip address after each transfer The number of transfers of whole data movement, where each transfer moves A_size of bytes. Starting address Size of each transfer; 1, 2, 4 are possible. Skip address after each transfer The number of transfers of whole data movement, where each transfer moves A_size of bytes.

2.1 Control DMA through CSR The structure of DMA CSR given in Table 1 can be seen as follow in terms of C program such that each register occupies 4-byte memory. It is given in sw/code/dma.h file. typedef struct { // DMA controller CSR UintT control; // {go, dir, ie} UintT status; // {busy, irq} UintT a_start; // start address UintT a_size; // size of item: 1, 2, 4 UintT a_stride; // skip UintT a_leng; // num of items UintT b_start; // start address UintT b_size; // size of item: 1, 2, 4 UintT b_stride; // skip UintT b_leng; // num of items } dma_t;

When address of DMA hardware is given, each register in the DMA can be accessed as follows, where AhbWrite()/AhbRead() are API routine to communicate ahb_trx and more details can be found from section 4.1. dma_t * dma = (dma_t*)0x00400000; AhbWrite(&dma->control, &data); AhbRead(&dma->status, &data);

A typical DMA control steps using interrupt mechanism can be as follows, where CSR_WRITE()/CSR_READ() are macro definition and actually use

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AhbWrite()/AhbRead(). More details can be found dma_api.h and dma_api.c in sw/code directory. // interrupt utilized DMA control // dma_set() API CSR_WRITE(dma->a_start , a_start ); CSR_WRITE(dma->a_size , a_size ); CSR_WRITE(dma->a_stride, a_stride); CSR_WRITE(dma->a_leng , a_leng ); CSR_WRITE(dma->b_start , b_start ); CSR_WRITE(dma->b_size , b_size ); CSR_WRITE(dma->b_stride, b_stride); CSR_WRITE(dma->b_leng , b_leng ); val = DMA_CONTROL_GO | DMA_CONTROL_DIR_A2B | DMA_CONTROL_IEI_ENABLE; CSR_WRITE(dma->control , val); // dma_wait_irq() do { interrupt = CheckInterrupt(); } while ((interrupt&1)==1); // dma_clear_irq() val = DMA_STATUS_IRQ_CLEAR; CSR_WRITE(dma->status , val);

A typical DMA control steps can be as follows, where register polling is used. // interrupt utilized DMA control // dma_set() API CSR_WRITE(dma->a_start , a_start ); CSR_WRITE(dma->a_size , a_size ); CSR_WRITE(dma->a_stride, a_stride); CSR_WRITE(dma->a_leng , a_leng ); CSR_WRITE(dma->b_start , b_start ); CSR_WRITE(dma->b_size , b_size ); CSR_WRITE(dma->b_stride, b_stride); CSR_WRITE(dma->b_leng , b_leng ); val = DMA_CONTROL_GO | DMA_CONTROL_DIR_A2B | DMA_CONTROL_IEI_DISABLE; CSR_WRITE(dma->control , val); // dma_wait_done() do { CSR_READ(dma->control, val); } while (val&DMA_CONTROL_GO);

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3 Hardware blocks in the FPGA

As shown in Figure 3, the FPGA in the iNCITE contains several hardware design blocks as follows. HIU: A design block takes care of connecting the iNCITE iCONUSB to the design in the FPGA, where iNCITE iCON-USB is the USB interface built in iNCITE board. Not shown here, but it locates at the left-hand-side of ahb_trx. ahb_trx: A design block generates AMBA AHB[6] bus transactions under the control of the commands received through the HIU. It is AMBA AHB BFM or transactor. ahb_sram_if_dual: A design block provides SSRAM interface such that it receives AHB transactions and accesses SSRAM accordingly. Especially, this block provides dual AHB slave ports. ahb_dma: DMA design block

Figure 3 : Hardware blocks in the FPGA of iNCITE

3.1 Control command of ahb_trx There are three basic data path between HIU and ahb_trx, which are C-FIFO, R-FIFO and W-FIFO. For more information how to communicate the transactor with HIU, refer to reference [3]. The ahb_trx received control commands through C-FIFO, where the control command consists of two 32-bit data; one contains all necessary information for AHB bus transaction and the other contains address as shown in Figure 4. CMD0[31]: IE internal or external access 0: external, i.e., AHB transaction 1: internal, i.e., access to the resource in the ahb_trx CMD0[30:27]: IA internal address CMD0[26:23]: ID internal data CMD0[21:18]: PR Protection Control (HPROT) CMD0[17:8]: BL Burst Length Single access should be 1 with BM 0

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ahb_sram_if_dual

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Burst access should be greater than 1, where BM should be 1 and TS should be 10 CMD0[6]: Locked transfer (LOCK) CMD0[5:3]: BM Burst Mode (HBURST) 0: single access 1: unspecified length access CMD0[2:1]: TS Transfer Size (HSIZE) 0: for byte 1: for short 2: word CMD0[0]: RW Read/write 0: read 1: write

Figure 4: ahb_trx command format Note that as the abh_trx is a simplified version, it only supports a single access and a burst access with unspecified length.1 The ahb_trx receives data stream through R-FIFO for read transaction and sends data stream through W-FIFO for write transaction.

4 Software components
For this example, there are two sets of API (Application Programming Interface); one is AHB transactor API and the other is Flash API. 4.1 AHB transactor API There is a set of API that controls ahb_trx as follows. void AhbWrite(UintT addr, UintT *data, UintT size, UintT length); void AhbRead (UintT addr, UintT *data, UintT size, UintT length); Those API will be found in bfm_api.h and bfm_api.c.

5 Design steps
1

The unspecified length transaction command causes the ahb_trx generates a series of single accesses.

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As Figure 1 shows, both hardware and software are required, where hardware is explained in Figure 3 and software is explained in section 4. 5.1 Prerequisites The followings are required. ModelSim-XE for logic simulation Xilinx WebPACK for logic synthesis and P&R Dynalith iNCITE and USB cable Dynalith iNSPIRE-Lite Visual Studio 6.0 or GNU tool chain on Cygwin 5.2 Directory structure Directory structure is as follows. hw directory contains hardware related files o amba_soc directory contains design shown in Figure 3, except SSRAM. verilog directory contains amba_soc.v. o inspire directory is working directory for iNSPIRE, which is a software used to prepare FPGA. o ip directory contains all design blocks which are used in amba_soc found in amba_soc/verilog directory. ahb_dma: DMA design ahb_sram_if_dual: Dual-port SSRM interface block ahb_trx: AHB TRX, refer section 3.1. amba_ahb: AMBA bus design sw directory contains software related files o code directory contains for C program to test DMA. main.c arg_parser.c init_fpga.c bfm_api.h/bfm_api.c mem_api.h/mem_api.c dma.h/dma_api.h/dma_api.c dma_test.c o run directory is working directory for compilation and emulation. 5.3 Hardware design flow hw directory is the working directory for this hardware design flow. Design step: Go to each design directory under the ip directory. Have a look; design file resides in rtl/verilog directory in the each design directory. Simulation step: Go to each design directory under the ip directory.

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Run simulation in sim/modelsim directory in the each design directory, if any. Go to amba_soc/sim/modelsim directory and run RunMe.bat or make with Makefile. Synthesis step: Go to amba_soc/syn/xst directory Run make.bat amba_soc.edif in amba_soc/syn directory is the result iNSPIRE step: Go to inspire directory Invoke iNSPIRE or iNSPIRE-Lite with project.nsp Follow iNSPIRE design flow fpga0.eif in inspire/par director is the result 5.4 Software design flow sw directory is the working directory for this software design flow.
5.4.1 Design steps

Design step Go to sw directory and have a look at the following program files. - main.c: main program - arg_parser.c: argument parsing program - init_incite.c: iNCITE initialization program - bfm_api.c: AHB transactor API program - dma_api.c: DMA API program - dma_test.c: DMA testing program Compilation step: follow one of below Run make with Makefile on Cygwin Run RunMe.bat, which invoke nmake with Makefile.vc Invoke Visual Studioi 6.0 with flash_test.dsw Running step Connect iNCITE to USB Turn on iNCITE Run dma_test.exe

6 Summary
This document addresses a simple DMA and how to verify its functionality using iNCITE.

References
[1] [2] [3] iNCITE User Manual, Dynalith Systems, www.dynalith.com. iNSPIRE User Manual, Dynalith Systems. iPROVE Transactor Design Manual, Dynalith Systems.

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[4] [5] [6]

iPROVE Transactor simulator Guide, Dynalith Systems. A Simple DMA Controller Specification, DS-AN-2007-10-001, Dynalith Systems, 2007.10. AMBA Specification, Rev. 2.0, ARM, www.arm.com.

Revision history
Oct. 31, 2007: Version 1 Revision 0 is prepared by Ando Ki.

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