designfeature By Ken Jaramillo and Subbu Meiyappan, Philips Semiconductors

PART ONE OF THIS SERIES REVIEWS BASIC SCAN-TEST TECHNIQUES. PART TWO PRESENTS 10 DESIGN PRINCIPLES TO FOLLOW FOR SUCCESSFUL IMPLEMENTATION OF THOSE TECHNIQUES.

10 tips for successful scan design: part two

O
nce you know the basics of scan design (see sible, never implement designs with internal tristate 10 tips for successful scan design: part one, bus structures. If you cant follow this rule, then impg 67), youre ready to take some action. The plement the fewest possible internal tristate-bus following list includes the most important issues to structures and guarantee by design that no bus conbe aware of to guarantee successful adoption of scan tention can occur on any internal bus during scan techniques within your company or design group: testing. Handle internal tristate buses with care and Two control problems require careful consideraavoid bus contention by design. tion. First, you must ensure that there is no con Make all clocks and asynchronous resets come tention on the tristate buses during scan-shift operfrom chip pins during scan mode. ations. Most scan-insertion tools can automatically Ensure that all scan elements on a scan chain perform this task during the scan-insertion phase. are in the same clock domain. Second, you must ensure that there is no possible Know the requirements and limitations of your contention on the internal tristate buses during the chip testers. capture cycles during scan testing. Handle mixing flip-flops triggered off different With most designs, you can generate a scan-test edges of the clock with care. pattern that causes bus contention on some inter Break all combinational-logic feedback loops. nal buses. Several ATPG tools are intelligent enough Handle all nonscan elements with care. to avoid generating patterns that cause bus con Avoid design practices that lead to non- tention. However, although the tools may be intelliscannable elements. gent enough to avoid contention, this intelligence Handle multiple clock domains Figure 1 with care to POTENTIAL BUS CONTENTION DURING SCAN TESTING BLOCK A avoid potential timing problems. Plan chip-level scan FUNCTIONAL INPUT 0 issues before you BLOCK B SCAN INPUT 1 start block-level design.
SCAN ENABLE CLOCK SCAN ENABLE CLOCK FUNCTIONAL INPUT SCAN INPUT SCAN ENABLE CLOCK 0 1

INTERNAL TRISTATE BUSES Without a doubt, the biggest hurdle to overcome in system-on-chip (SOC) designs with respect to automatic test-pattern generation (ATPG) is the proper control of internal tristate bus structures. If poswww.ednmag.com

When two flip-flops control the output enable for bus transceivers, bus contention can occur. February 17, 2000 | edn 77

designfeature Scan design

takes a fair amount of CPU effort. DeFUNCTIONAL pending on the design, the ATPG INPUT 0 Figure 2 effort could be so CPU- intensive SCAN INPUT 1 that it results in longer runtimes, fewer FUNCTIONAL INPUT patterns, and lower fault coverage. If the SCAN ENABLE ATPG tool cannot identify scan-test patterns that create bus contention and uses CLOCK CLOCK (a) those vectors to test the device, then the part may be stressed during the producFUNCTIONAL tion test. This production-test stress may INPUT cause the part to fail on the tester, cause FUNCTIONAL damage, or cause a shortened life cycle. INPUT 0 Therefore, avoiding contention on interSCAN INPUT 1 nal tristate buses is important. Bus-contention problems in SOC deSCAN ENABLE signs occur at two levels. The first prob(b) CLOCK lem is within a design block that contains multiple drivers to a tristate port. The second problem is at the chip level, in Two design practices to avoid are using one flip-flop in the scan chain to drive the asynchronous set which multiple blocks interface to the or clear of another flip-flop (a) and using one flip-flop in the scan chain to drive the clock of another same bus. Consider the case of an interflip-flop (b). nal PCI-bus structure. In normal operation, bus-arbitration logic via the request/grant pairs guarantees that only LOCKUP LATCH one master controls the bus at a time. During scan testing, however, the ATPG SCAN INPUT EN tool easily generates test patterns that would turn on multiple requests, grants, BLOCK B BLOCK A and output-enable signals for bus transCLOCK ceivers, thus forcing multiple devices onto the tristate bus simultaneously. In Figure 1, two blocks drive Figure 3 a common internal tristate bus. The figure represents a single bit of the If the design includes falling-edge-triggered flip-flops, place all of these flip-flops at the beginning of bus. In each block, scan flip-flops control the scan chain for each block and insert lockup latches between blocks. the output enables for the bus transceivers. The last flip-flop in Block As scan sets come from chip pins during scan around the scan chain, the second flipchain drives the first flip-flop in Block Bs testing to allow the ATPG tool to control flop resets set or clear depending on the scan chain. If the ATPG tool generates a clocks and resets in the design. Neglect- shift data. The ATPG tools cannot propattern that causes both flip-flops to shift ing this fact will cause the ATPG tool to duce useful scan patterns for this type of in values of zero, then you have bus con- consider each potential scan element that circuit. Thus, the tool doesnt include the does not have a clock or reset coming second flip-flop in the scan chain and tention on this bit of the bus. Although there are several approach- from a chip pin as unscannable. The tool considers this flip-flop as an unknown es to these types of problems, the solu- considers all unscannable cells as un- during pattern generation, resulting in a tions are generally simple. (You can knowns during pattern generation, re- loss of fault coverage. If this type of logdownload the appendix Internal PCI- sulting in reduced fault coverage. ic exists, you should insert a multiplexer This suggestion does not imply that all in the reset path of the second flip-flop. bus-contention solution from EDNs Web site, www.ednmag.com/ednmag/ clocks and resets must come directly This multiplexer allows a chip pin to conreg/2000/02172000/04ms604.htm) It is from pins. Rather, the ATPG tool must trol the reset signal during scan test or important to recognize that if you use in- have total control of scan-element clock disables the reset pin of the flip-flop. ternal buses, you must guarantee by de- and reset signals. The tool must be able In general, you want to avoid any asynsign that bus contention is impossible to control the clocks and be able to de- chronous flip-flop input that a chip-levassert the resets. The following examples el reset pin cant disable. Therefore, if an during scan testing. demonstrate this situation. asynchronous-reset input of a flip-flop CLOCKS AND ASYNCHRONOUS RESETS Figure 2a shows one flip-flop in the ties to the output of some combinationThe next biggest issue when it comes scan chain driving the asynchronous set al logic that a chip-level reset pin cannot to achieving high fault coverage is to en- or clear pin of another flip-flop.You must disable (the logic may have scan flip-flop sure that all clocks and asynchronous re- avoid this design practice. As data shifts outputs as its inputs or even chip-level

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inputs), then you must insert flops apiece. Each scan chain a multiplexer. Note requires a test pattern that is Figure 4 IC1 that if the offending 1000 bits long for each test signals that prevent a single pattern, even though the chip-reset pin from disabling chains that are two flip-flops the flip-flops asynchronous long have patterns that conIC6 input are chip pins, then you tain 998 dont-care bits and IC3 can solve the problem by forconly two real-test bits. So, it IC2 ing the ATPG tool to drive may be wise to break some IC5 these pins to constant values of the longest chains into during pattern generation. multiple chains. If you deIC4 This approach is easier than cide to combine scan chains adding multiplex circuitry. based on different clocks Figure 2b shows one flipto equalize the scan-chain flop in the scan chain driving lengths or to compensate for the clock input of another Combinational feedback loops, from IC6 to IC3 in this case, can produce an tester limitations, for examflip-flop. You must also avoid unstable output. You need to break this loop during scan mode for the plemake sure you place this design practice if possi- ATPG tool to predict the operation of the circuit. lockup latches between the ble. As data shifts around the scan chains to avoid potenscan chain, the second flip-flops clock cant control. Therefore, if a flip-flops tial hold-time problems. toggles, depending on the shift data. The clock input ties to the output of some It is also a good idea to include lockup ATPG tools cannot produce useful scan combinational logic that a single chip- latches between chip-level blocks even if patterns for this type of circuit. Thus, the level clock pin cannot control, then you the blocks are in the same clock domains. scan chain does not include the second need to insert multiplex circuitry, just as Inserting these latches is unnecessary if flip-flop, and the tool considers this flip- in the previous example. The logic may youve done an accurate static-timing flop as an unknown during pattern gen- have scan flip-flop outputs as its inputs, analysis, but using the latches minimize eration, resulting in a loss of fault cover- chip-level inputs, and even chip-level the chances for hold-time problems beage. clock inputs. If the offending signals that tween blocks. Preventing hold-time This type of design exists for circuits prevent a clock pin from controlling the problems is important because most of such as clock dividers. Therefore, if this flip-flops clock input are themselves chip the effort relating to scan begins after you type of logic exists, you have two options. pins, then you can force the ATPG tool to deliver a final netlist for placement and First, you can insert a multiplexer in the drive these pins to constant values dur- routing of the chip. Also, you typically clock path of the second flip-flop such ing pattern generation. This approach is develop static timing scripts for scan that the clock input ties to one of the scan easier than adding multiplex circuitry. paths after the development of scripts to clocks only during scan-test mode. Beverify functional paths. Adding these cause this approach introduces logic in SCAN ELEMENTS lockup latches adds few gates to the dethe clock path, the clocks between the Several factors determine the number sign, and the latches help to avoid poflip-flops are no longer synchronous. of scan chains in a design. In general, you tential timing problems that you might Therefore, you should insert a lockup want to divide scan chains by clock do- not find until late in the design cycle. latch in the scan chain before and after main. All flip-flops in a scan chain should the second flip-flop to avoid any poten- use the same clock. However, some factors REQUIREMENTS OF CHIP TESTERS tial hold-time problems. If several in- might make this situation undesirable. You have to know the limitations of stances of this circuit exist, you may want First, each scan chain must have its own your production tester before you can to create a clock that all these flip-flops scan-input and -output pin. The more plan an effective strategy for scan. Two can use during scan-test mode. In this scan chains you have, the more pins you limits impact test. The first is test time. In case, you would need to place a lockup must set aside for test. If you dont dedi- general, you should design production latch only before the first and the last of cate pins for test, you must dedicate logic tests to operate in less than 3 sec, roughthese flip-flops. to multiplex the scan inputs and outputs ly the cycle time of the device handler. Second, you can insert a multiplexer in with other chip pins. Also, the production Tests that take longer than 3 sec result in the second flip-flops asynchronous re- tester that tests the chips has limitations excess cost per chip. The second limit to set path to tie this flip-flop active, which that affect the number of scan chains a de- keep in mind is tester memory. The enholds the flip-flop in reset only during sign can support. Finally, it is generally a tire test program must fit into the availscan-test mode. This approach is less ef- good idea to equalize scan-chain lengths. able memory of the tester. You can nevfective than the first one but is better than Remember that each scan pattern is as er reload test memory in the middle of having the ATPG tool consider the sec- long as the longest scan chain. the test. Dedicated scan-hardware conond flip-flop as an unknown. For example, consider a design with 10 straints limit most testers to a certain In general, you want to avoid any clock scan chains, one chain being 1000 flip- number of scan chains. Table 1 shows input that a single chip-level clock pin flops long and the rest being two flip- one possible configuration of an exam-

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ple tester with 128 Mbits of memory. scan data value after a shift cycle. quiring that you add lockup latches beIn Table 1, the example tester supports Fortunately, handling a situation in fore and after these flip-flops in the scan a maximum of 32 scan chains. The num- which several blocks within a chip may chain. ber of scan chains you choose determines have falling-edge-triggered flip-flops how much memory you have to work doesnt mean that you have to place all COMBINATIONAL-LOGIC FEEDBACK LOOPS with, which directly impacts the number falling-edge-triggered flip-flops at the Designs that contain combinationalof test patterns the tester can support. front of the entire scan chain, which con- feedback loops have inherent testability Most testers work on even problems. Combinationnumbers of scan chains. For exfeedback loops may introTABLE 1POSSIBLE TESTER MEMORY CONFIGURATIONS ample, if a design has nine scan duce internal logic states to Maximum number of scan chains Available memory per chain (Mbits) chains, the available memory a design that scan-storage One 128 per chain is still 8 Mbytes; the elements cannot control. Two 64 remaining memory is inaccesConsider a circuit with Four 32 sible for the scan test. three flip-flops and a comEight 16 The following example binational feedback loop 16 8 shows how to determine the from IC6 to IC3 (Figure 4). 32 4 This feedback loop causes number of allowable test patterns you can generate based on the sists of multiple chip-level blocks. When- the problem. If you initialize the flip-flops testers memory limits: ever a falling-edge-triggered flip-flop fol- to values of IC1 0, IC2 0, and IC4 1, Tester_Memory_Per_Chain lows a rising-edge-triggered flip-flop in then the output at IC6 will be a stable high. (#Scan_PatternsMax_Scan_Chain_L a scan chain, you must insert a lockup If IC2 changes to a logic high, then the outength) Max_Scan_Chain_Length. latch between them. The lockup latch put at IC6 oscillates between 0 and 1. BeTester_Memory_Per_Chain To- prevents data from shifting through both cause of this oscillation, ATPG tools cantal_Tester_Memory/Number_Of_Scan- flip-flops in one clock cycle. To avoid not predict the operation of the circuit. To chains. having an excessive amount of lockup generate patterns, the ATPG tool would Number_Of_Scanchains is in multiple latches, it is still advisable to place all the have to break this loop, which would reof two increments (except if you have falling-edge-triggered flip-flops at the duce overall fault coverage. ATPG tools only one scan chain). beginning of the scan chain for each have a few methods for breaking combi1 Mbyte of memory 1,048,576 bits. block. Then, you need to place lockup national feedback loops. Some of these #Scan_Patterns (Tester_Memory_ latches only between blocks. Figure 3 methods are less harmful to fault coverPer_Chain Max_Scan_Chain_Length)/ shows two chip-level blocks, A and B, age than others, but all of them result in Max_Scan_Chain_Length. each containing falling-edge-triggered some loss of coverage. Therefore, you For example, if the amount of memo- flip-flops. The blocks scan ports connect should avoid combinational feedback ry available on the tester is 256 Mbytes, together via lockup latches at the chip loops whenever possible. Most ATPG tools inform users of all the combinayour design has eight scan chains, and level. your longest scan chain is 3000 flip-flops A few ATPG tools have difficulty han- tional-feedback loops present in a design. If you cannot avoid these feedback long, then dling falling-edge-triggered flip-flops Tester_Memory_Per_Chain 256 during capture cycles and may require loops, then you should break the feedMbits/8 33,554,432 bits 32 Mbits. special commands to inform the tool back loop by inserting an additional flip#Scan_Patterns (33,554,432 3000)/ how to handle the 3000 11,183 ATPG patterns. flip-flops. You should This example shows how to calculate investigate how your SYSTEM MEMORY tester-memory limitations. These calcu- ATPG tool handles lations depend on the type of tester you this situation. You LOCAL MEMORY BUS (FOR EXAMPLE, PCI) use. You should consult the test-engi- may even consider neering personnel of your testers manu- changing the Figure 5 A facturer for details. circuit so that these flip-flops trigMIXING FLIP-FLOPS ger off the rising edge LOGIC NECESSARY TO TAKE FIFO DATA FROM NETWORK AND ATPG tools require that you place all of the clock during PLACE IN SYSTEM MEMORY falling-edge-triggered flip-flops at the scan mode rather front of a scan chain. If you place a than off the falling B falling-edge-triggered flip-flop after a ris- edge. But remember, ing-edge-triggered flip-flop in the scan modifying the clock NETWORK (IEEE 1394 FIREWIRE, ETHERNET, AND OTHERS) chain, a single clock cycle will clock scan inputs of these flipdata through both flip-flops. This situa- flops effectively puts tion causes some loss of coverage because them in a different You need to carefully handle the FIFO to be able to test the surroundthe two flip-flops always have the same clock domain, re- ing logic blocks, A and B.

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flop that is present in OE_N the feedback path only SCANTESTMODE during scan-test mode. This modificaCS_N Figure 6 tion results in WE_N the highest fault coverADDRESS[M:O] age. If you cannot insert DATA[N:O] a flip-flop, then insert a multiplexer in the feedback path that drives a (a) constant value during scan-test mode. This OE_N approach results in lowSCANTESTMODE er coverage than the flip-flop option but CS_N higher coverage than if WE_N you allow the tool to ADDRESS[M:O] break the loop by asDATA_IN[N:O] suming an unknown DATA_OUT[N:O] value as a result of the loop. the other. In this case, the test doesnt include the logic surrounding the CS_N FIFO array unless you WE_N use special techniques to make the FIFO ATPGADDRESS tool-friendly. Figure 5 D shows an example of a RAM array (FIFO) for a RAM (WITH BIDIRECTIONAL networking application. DATA BUS) The logic in A and B grabs the data off the network and places it in OE_N system memory. If you CS_N dont handle the FIFO WE_N carefully, you could lose ADDRESS a lot of fault coverage. You need to design the DIN FIFO so that you can obDOUT serve the outputs from RAM the logic in B and control (WITH UNIDIRECTIONAL (b) DATA BUS) the inputs to logic A durNONSCAN ELEMENTS ing scan-test mode. Scan-insertion tools Several techniques can CS_N consider all cells that do increase the observabiliCS_N WE_N not have a scan-equivaty of logic immediately WE_N ADDRESS lent cell as black boxes before the RAM and inADDRESS[M:O] DIN and do not insert them crease the controllabiliinto a scan chain. ATPG ty of logic immediately DOUT DATA[N:O] tools consider sequenafter the RAM. Support tial cells that are not on for these techniques RAM OE_N scan chains as black varies among ATPG (WITH UNIDIRECTIONAL SCANTESTMODE boxes. Therefore, you tools. So, investigate your DATA BUS) (c) must treat all nonscan ATPG tools capabilities sequential elements Deasserting the output enable during scan-test mode isolates RAM with bidirectional before you decide how to with care to avoid loss of (a) and unidirectional data buses (b, c). handle RAM. Keep in fault coverage. Exammind that there are ples of nonscan elements are latches, flip-flops, latches, and combination-log- many types of RAM blocks. Some have RAM, and design blocks that do not in- ic gates. Thus, scan techniques do not bidirectional data buses, and others have clude scan. verify RAM circuits during production unidirectional data buses. Some are synAlthough latch-based designs are pop- testing. Instead, you use RAM built-in chronous, and others are asynchronous. ular for gate and power savings, most self-test (BIST) to verify RAM cells. This The best technique to use depends on scan/ATPG tools do not handle these de- technique involves writing several pat- your application and your vendor library. signs optimally. ATPG tools can under- terns into the RAM array to check for the The approach you ultimately choose destand the behavior of latches that the de- various failure modes of RAM cells. BIST pends on your design architecture (a sinsign holds transparent, but these tools is a well-known technique. (See Refer- gle bidirectional bus or two unidirecmodel the behavior of latches when they ence 2 for an introduction to BIST and tional buses), your timing budget are not transparent as unknowns. If the testing of RAM and ROM.) (whether the design can withstand addilatch data feeds into other logic that a Because you test RAM via BIST, which tional logic in the datapaths), and your scanned register then captures, poor fault achieves high fault coverage, ATPG tools ATPG tool (whether it supports modelcoverage could result. In general, you need not test and fault-grade RAM. ing of RAMs). should keep all latches transparent dur- However, even though BIST logic makes There are five ways to deal with RAM. ing scan testing, but you should investi- RAM fully testable, a large reduction in The first and easiest approach is to isogate how your scan/ATPG tool handles test coverage of the surrounding logic late the RAM block by deasserting its latches. may result. This reduction is commonly output-enable signal during scan mode. RAM cells have more complex failure known as the shadow effect. Imagine a This method adds no observability or modes than do the simple stuck-at FIFO array for which surrounding logic controllability for the RAM, but it gets modes for standard-cell logic, such as pushes data in one side and pulls data out the RAM off the bus so that it does not
OE_N

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interfere with the other blocks on the data bus. Implementation depends on the type of RAM the design uses. Figure 6a shows the logic necessary to isolate a RAM that has a bidirectional bus using the RAMs output-enable signal. Figure 6b is similar to Figure 6a except the RAM has separate data-in and data-out buses, and the design uses these buses separately. Figure 6c is similar to Figure 6b in that the RAM has separate data-in and -out buses, but this implementation combines the data buses into one bidirectional data bus. The second approach is to isolate the RAM block by inserting a multiplexer to drive the data signals during scan mode. The drive values can be either constant or some combination of the input-control signals. This approach is useful only for RAM blocks with unidirectional read-and-write data buses, but it is more sophisticated than the previous approach, which simply disables the RAM. In this case, you allow the test to drive a constant pattern onto the output data bus. Thus, this approach adds controllability to the logic immediately after the RAM because the ATPG tool can affect the output data of the RAM, although only in a simple way. Figure 7a shows an implementation using unidirectional data buses; Figure 7b uses a bidirectional data bus. Both figures show a RAM block that has unidirectional data buses. Third, you can place the RAM block into a transparent mode during scan test (Figure 8). In this mode, you essentially route data-in to data-out. Note that this approach is only useful for RAM blocks with unidirectional read-and-write buses and with designs that use the buses separately. This solution not only provides controllability of the logic immediately after the RAM, as in the previous approach, but also provides observability to the logic immediately before the RAM. A fourth approach is to write RAM data before scan test and use the RAM contents to generate test data for the surrounding logic during scan test. To avoid disturbing the RAM contents during scan test, disable the RAM write signal during scan-test mode. This method requires the ATPG tool to support a functional RAM model. Some ATPG tools allow for only a partial initialization of the RAM array. This approach adds a lot of controllability to the logic immediately after the RAM but no observability to the logic before the RAM. Another drawback is the length of time that initializing the RAM array might require. Yet another potential drawback is that this approach requires the ATPG tool to support a functional RAM model. Because many ATPG tools support RAM models, this issue may not be critical. Figure 9a shows the implementation for which you must initialize the entire RAM before scan testing and then allow the contents of the RAM to test the surrounding logic. Figure 9b shows the implementation for which you need initialize only a single location within the RAM before scan testing. This approach saves time on initialization but provides less controllability than the logic in Figure 9a. You can create an approach between these two that requires initialization of only a certain number of locations, for example, the bottom 1 kbyte of memory. The fifth approach is to leave the RAM as is and let the ATPG tool functionally exercise it to generate logic values to test the surrounding logic during scan test. This method requires that the ATPG tool supports a functional-RAM model. This approach requires no changes to the hardware and provides the most observability of the logic before the RAM and controllability of the logic after the RAM. However, this approach requires an ATPG tool that can model RAMs and a little more effort to learn how to use it. Portions of your chip may not include scan circuitry. Examples are older versions of blocks and third-party intellectual property.You can test these blocks by using canned test vectors, logic BIST, or other testing methods. However, you need to be careful that the lack of scan in these blocks does not hurt the ability to test other blocks in the chip. You can use multiplexer-isolation techniques to separate any nonscan blocks from the scan section of the design during scan mode. Well-designed scan and nonscan isolation with appropriate control logic reRAM (WITH UNIDIRECTIONAL DATA BUS)

Figure 7
OE_N

RAM (WITH UNIDIRECTIONAL DATA BUS)

CS_N OE_N CS_N CS_N WE_N ADDRESS ADDRESS[M:O] DATA_IN[N:O] DIN DIN WE_N WE_N ADDRESS[M:O] ADDRESS CS_N WE_N

1
DATA_OUT[N:O]

DOUT DATA[N:O]

0 1

DOUT

CONSTANT VALUE OE_N

SCANTESTMODE

SCANTESTMODE

(a)

(b)

CONSTANT VALUE

You can isolate RAM during scan test by driving output data to a constant value in the case of both unidirectional (a) and bidirectional (b) data buses.

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RAM sults in fast and trouble-free test-pro(WITH UNIDIRECTIONAL DATA BUS) gram generation with high fault Figure 8 coverage. To increase the fault coverage that you can obtain from scan OE_N ATPG software, the isolation circuitry of OE_N CS_N nonscanned blocks should set the outputs of such blocks to known logic states CS_N WE_N during scan mode. WE_N Examples of nonscanned flip-flops are ADDRESS flip-flops that have no scan equivalent ADDRESS[M:O] and thus cant be part of the scan chain. DIN DATA_IN[N:O] Nonscanned flip-flops can also be flipflops that you design into the circuit such 1 DATA_OUT[N:O] DOUT that you could not place them on a scan chain because of improper generation of clock or reset inputs (see tip 2). You 0 should first try to fix the cause of the problem. For example, if the flip-flop has SCANTESTMODE no scan-equivalent cell in the ASIC library, then change the design so that it Routing data in to data out during scan test places RAM in transparent mode. uses a scan-type flip-flop instead. If problems exist with the generation of the tied to the same clock line. The same You can avoid potential hold-time clock or reset inputs, then change the de- clock tree must generate this clock line. problems by ensuring that a scan chain sign according to the recommendations If two flip-flops use clocks that come consists only of flip-flops from the same in tip 2. If you cant modify the design, from the same clock tree but a different clock domain. If this situation is not feathe last resort is to design access to the branch of the tree, you still consider them sible, then you should add lockup latchpreset or clear connectors such that the within the same clock domain as long as es between the adjacent flip-flops on a system, or tester, holds the flip-flops in you carefully watch your clock skew. scan chain that are in different clock doknown states, either preset active or clear However, if one flip-flop takes the clock mains. To avoid having too many lockactive, during scan mode. This approach directly from the clock tree and another up latches and a confusing scan-chain insomewhat reduces fault coverage because flip-flop has to modify the clock via com- terconnect, you should analyze your it limits the controllability of input nodes binational logic, then the two flip-flops designs beforehand to avoid any gating of of the flip-flop and of the logic down- are in two clock domains. The only way clocks. If you cant avoid clock gating, you could consider these clocks as in the then attempt to minimize it. Try to destream from the flip-flop. same clock domain is if you carefully velop a scheme that localizes all of the NONSCANNABLE ELEMENTS watch the clock skew between them, as- clock gating so that these flip-flops use The ASIC vendor and library you suming that they are next to each other the same clock during scan mode, meanchoose dictate the types of scan-equiva- in the scan chain. ing they are within the same clock dolent cells you can design with. Because Keeping an eye on clock skew is im- main for scan purposes. Then, you can most vendor libraries have a rich variety portant because, although its usually place the flip-flops together, and you of standard logic cells to choose, engi- easy to meet setup-timing requirements need to place lockup latches only before neers typically write HDL code to pro- during scan testing, due to slow scan- the first and after the last flip-flop in this duce sequential logic without paying clock frequency, hold-time problems are group. much attention to the types of available common. As you internally route the cells. However, the scan-insertion tools blocks scan chainsmeaning that you CHIP-LEVEL-SCAN ISSUES pick flip-flops that come from a subset of route the scan chains at the block level This final set of tips is simply a collecthis library. Currently, only one cell lacks and connect them at the chip level tion of issues that you need to think vendor libraries when it comes to scan: hold-time problems arent prevalent for about at the chip level to ensure the corflip-flops with both asynchronous set flip-flops in the same clock domain. Tim- rect handling of chip-level and block-levand asynchronous clear inputs. There- ing problems usually occur between el scan issues. fore, avoid designing functions that re- blocks, due to the distance between log Route the scan chains at the block quire these types of cells. Scan flip-flops ically adjacent scan flip-flops, which level and connect them at the chip usually have either an asynchronous set causes excessive clock skew, and within level. To avoid potential hold-time or an asynchronous clear but not both. blocks, in which clock-gating occurs. Any problems, consider using lockup gating of the clockwhether for power latches at the chip level to hook up MULTIPLE CLOCK DOMAINS savings or for multiplexing to handle isthe scan chains between blocks. It is important to handle multiple sues with the second scan-test technique, Dedicate pins to handle the scan clock domains with care. A clock domain for exampleintroduces skew in the chains using scan-enable, scan-inis a grouping of sequential elements all clock line. put, scan-output, and scan-test-

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designfeature Scan design

mode signals, or design logic to WE_N multiplex the scan pins with the WE_N SCANTESTMODE normal functional I/O. CS_N Preplan all the various test Figure 9 CS_N modes you need and deterOE_N mine how to get the chip into those OE_N modes. You can either use spare ADDRESS pins or design in logic, such as testADDRESS[M:O] access-port controllers (Reference 1). This test logic needs to at least DIN DATA_IN[N:O] generate a scantestmode signal to alert logic in the chip when scanDOUT DATA_OUT[N:O] test mode is active. All of the various multiplex logic that this article RAM mentions uses this signal to bypass (a) (WITH UNIDIRECTIONAL nonscan blocks, to multiplex clock DATA BUS) signals to clock pins of flip-flops, and to multiplex reset signals to set WE_N WE_N or clear pins of flip-flops. SCANTESTMODE Buffer the scan-enable signal to CS_N CS_N provide the maximum scan-testing frequency. Remember that every OE_N OE_N flip-flop uses the scan-enable signal. If youre not careful, you could ADDRESS[M:O] 0 end up with a large ramp time on ADDRESS this signal. A few 4 drive buffers 1 0 in parallel should be able to drive more than 20,000 gates to run the DATA_IN[N:O] DIN scan vectors at 20 MHz. If higher speeds or more flip-flops are inDOUT DATA_OUT[N:O] volved, then a little more buffering is necessary. Although 1 MHz is a RAM (WITH UNIDIRECTIONAL typical scan frequency, it may be (b) DATA BUS) necessary to increase the frequency, to 10 or 50 MHz, for example, for the production-test vectors to run Another way to test surrounding logic is to preinitialize the entire RAM (a) or one location in RAM in a reasonable amount of time. (b) and then use the contents to generate test data for the logic. You can use the scantestmode The test frequency depends on the signal to disable the RAMs write signal during scan test. complexity of design, how scan friendly the design is, and how do not change the direction of bidirec- ics, high-speed serial buses, high-performmany scan patterns are necessary to tional I/Os as the result of a capture cy- ance gaming platforms, PCI-bus-related achieve the desired fault coverage. cle or do not cause any contention as a products, high-performance PC audio, and The design complexity limits the result of the bidirectional I/Os changing high-speed networking products. He has a BSEE from the University of Missouri speed of the test. A higher number to outputs. (Kansas City) and a BSCE from the Uniof scan patterns generally warrants versity of Missouri (Columbia). a higher test frequency, so that the References 1. IEEE Standard 1149.1-1990, IEEE test time remains as short as possiStandard Test Access Port and Boundary Subbu Meiyappan is a senior design engible. Handle bidirectional I/O with care. Scan Architecture, New York, IEEE, 1990. neer at VLSI Technology, a subsidiary of 2. ASIC/IC Design-for-Test Process Philips Semiconductors. He has worked for Bidirectional I/Os can cause problems on testers, depending on how freely the Guide, Mentor Graphics, www. the company for three years, designing, developing, synthesizing, simulating, and ATPG tool chooses to operate them. Fre- mentorgraphics.com validating high-performance intellectualquently, the default setting of the ATPG property blocks for PCI, ARM-ASB-based tool allows it to generate vectors in which Authors Bio graphies the bidirectional I/Os change direction as Ken Jaramillo is a principal engineer at devices, and high-performance ASICs. He a result of the capture clock. Production Philips Semiconductors, where he has has a BE from Annamalai University (Antesters do not generally support this ac- worked for four years. He has worked as namalai Nagar, India) and an MS from tivity. To be safe, you should instruct the designer and architect of ASICs, FPGAs, Tennessee Technological University ATPG tool to generate scan patterns that and boards for products including avion- (Cookeville, TN).

90 edn | February 17, 2000

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