Scribd Logo
Upload

Welcome to Scribd!

  • Verilg Subjective Examination - 1

    Uploaded by

    Rakesh Kumar
    9 views1 page
    Answer any Four of the following questions. (a) Give a brief notes on any three operators in Verilog HDL. (b) Write a Verilog code for an UP / DOWN counter.

    Original Description:

    Original Title

    Verilg Subjective Examination -1

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    Answer any Four of the following questions. (a) Give a brief notes on any three operators in Verilog HDL. (b) Write a Verilog code for an UP / DOWN counter.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    9 views1 page

    Verilg Subjective Examination - 1

    Uploaded by

    Rakesh Kumar
    Answer any Four of the following questions. (a) Give a brief notes on any three operators in Verilog HDL. (b) Write a Verilog code for an UP / DOWN counter.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    G.NARAYANAMMA INSTITUTE OF TECHNOLOGY AND SCIENCE SHAIKPET , HYDERABAD IV/IV B.

    Tech, 1ISEM, I SUBJECTIVE EXAMINATION Subject: Digital Design through Verilog HDL Branch: ECE-A &B Date: 01/02/11 Time : ( 10 :00 TO 11.30 AM) 4X5=20 [5M] [3M] [2M] [3M] Max marks-20

    Note: 1. Answer any Four of the following questions. 1. Explain syntax of module with an example clearly ? 2. a) Write a short notes on data types of Verilog HDL ? b) Differentiate Initial construct from always construct using an example. 3. (a) Give a brief notes on any three operators in Verilog HDL ?

    (b) Write a Verilog code for 4 to 1 multiplexer using conditional operator [2M] 4. (a) Design a Verilog module for an UP/DOWN counter ? (b) Design the Test 5. (a) Write about bench for the same module using Verilog HDL ? [3M] [2M] [3M]

    switch primitives of Verilog HDL ?

    (b) Write a Verilog code for CMOS Inverter

    using switch primitives [2M] [5M]

    6. Give the syntax for the following constructs of Verilog HDL a) Wait d) If-else-if b) Force-release e) Case Loop c) For Loop

    PAPER SET BY K.RAGINI AND V.RADHA KRISHNA Dep.Of.ECE, GNITS ********************** ALL THE BEST***************************************

    You might also like