Lab 5

Part II: Design and implement a circuit on DE1 kit that acts as a real-time clock

A.Theory
B. Create Quartus project
1. To Project Vo File chn New/ Verilog HDL File

Hnh 1. Chn ngn ng lp trnh

Xut hin giao din v ta bt u vit chng trnh nh sau

Hnh 2. Giao hin dng vit chng trnh 2. M t v chp hnh qu trnh gn chn, kt ni vi cc LED,

Hnh 3. S khi

Hnh 4. Gn chn
3. Hnh nh bin dch, bng tng hp kt qu v qu trnh np chip

Hnh 5. Qu trnh bin dch thnh cng

4. M phng : S dng phn mm Qsim

Bc 1: M Qsim bng cch vo Start - > run -> cmd Bc 2: Trong ca s command g: cd C:\altera\12.0sp2\quartus\bin ->Enter -> quartus_sh qsim Bc 3: Ca s Qsim hin ra. Vo menu File chn Open project, trong ca s nh hin ra chn n file project (*.qpf). Bc 4: Trong ca s Qsim, vo menu File, chn New Simnulation Input File v ta thy hin ra ca s Simulation Waveform Editor. Bc 5: Trong ca s Simulation Waveform Editor, vo Edit -> Insert -> Insert Node or Bus. Trong ca s Insert Node or Bus va hin ra, bm nt Node Finder tm cc chn input, ouput. Ca s Node Finder hin ra, bm nt list s hin ra tt c cc chn m ta thit k. Bm >> chn tt c chn ny. Bm OK -> OK. Bc 6: Trong ca s Simulation Waveform Editor, ta chn xung cho cc chn input bng cch click chn chn input v click vo loi xung trn thanh cng c Wavefom Editor. Sau , vo menu File -> Save as: chn ng dn lu file ny li. Bc 7: Quay tr li ca s Qsim. Vo menu Assign -> Simulation Setting -> Brown: chn file ta va lu lc ny. -> OK. Bc 8: Trong ca s Qsim, vo menu Processing -> Start Simulation. Ca s hin ra l kt qu m phng.

Hnh 6. Kt qu m phng