MEMORY DESIGN

I. II. III. IV. Tm hiu tng quan v Memory Yu cu thit k Specification Trin khai trn verilog

I.

Tm hiu tng quan v memory

clk data_out reset

memory

data_in

wire Cc thng s c trng ca b nh

Dung lng b nh: Tng s byte ca b nh ( nu tnh theo byte ) hoc l tng s bit trong b nh nu tnh theo bit. T chc b nh: S nh v s bit cho mi nh Thi gian thm nhp: Thi gian t lc a ra a ch ca nh n lc c c ni dung ca nh . Chu k b nh: Thi gian gia hai ln lin tip thm nhp b nh.

II.

III.

u vo:l cc ng a ch:An-1-A0 ->c 2n t nh. u ra:l cc ng d liu: Dm-1 D0 -> di t nh =m bit Dung lng chip nh =2n x m bit Cc ng iu khin: Tn hiu ch n chip CS (Chip Select) Tn hiu iu khin c OE (Output Enable) Tn hiu iu khin ghi WE (Write Enable) (Cc tn hi u iu khin th ng tch c c vi m c 0) Yu cu thit k - p ng theo yu cu ca bi tp ln,nhm chng thit k 2 bn nh l RAM v ROM nhng c dung lng nh. Specification Loi Input Input Input Input Input output M t 8-bit d liu vo 6-bit c a ch nh 6-bit ghi a ch nh Cho php ghi u vo u vo xung clock 8-bit d liu ra

Tn cng Data[7:0] Read_addr[5:0] Write_addr[5:0] We Clk Q[7:0]

IV.Trin Khai Trn Verilog module ram_infer ( input [7:0] data, input [5:0] read_addr, write_addr, input we, clk, output reg [7:0] q );

// Declare the RAM variable reg [7:0] ram[63:0];

always @ (posedge clk) begin // Write if (we) ram[write_addr] <= data;

// Read (if read_addr == write_addr, return OLD data). write) // in the write assignment. bypass

To return

// NEW data, use = (blocking write) rather than <= (non-blocking NOTE: NEW data may require extra

// logic around the RAM. q <= ram[read_addr]; end

endmodule