/*program for d-ff */ module assign_deassign (d,clk,q,reset_n,q_n); //module name. input d,clk,reset_n; //input port declaration .

output q,q_n; //output port declaration. reg q,q_n; always@(posedge clk,negedge reset_n) begin if (reset_n==0) begin //if reset is active. assign q=0; assign q_n=1; end else begin deassign q; deassign q_n; //if reset is not applied. q<=d; q_n<=!d; end end endmodule