module cnt_255 ( a, cnt_reg, cnt_start, cnt_reset, cnt_next, clk, reset_n); input a; input clk; input reset_n; output output

output output [7:0]cnt_reg; cnt_start; cnt_reset; [7:0]cnt_next;

reg [7:0]cnt_reg; wire cnt_start; wire cnt_reset; wire [7:0]cnt_next; assign cnt_reset= (cnt_reg==255); assign cnt_start= (a==1'd0); assign cnt_next = cnt_reg+1'b1; always@(posedge clk or negedge reset_n) begin if(reset_n==1'b0) cnt_reg<=8'd0; else if(cnt_reset==1'd1) cnt_reg<=8'd0; else if(cnt_start==1'd1) cnt_reg<=cnt_next; else cnt_reg<=cnt_reg; end endmodule